公开(公告)号：US20090077322A1

公开(公告)日：2009-03-19

申请号：US11857674

申请日：2007-09-19

申请人： Charles Ray Johns ,  Roy Moonseuk Kim ,  Peichun Peter Liu ,  Shigehiro Asano ,  Anushkumar Rengarajan

发明人： Charles Ray Johns ,  Roy Moonseuk Kim ,  Peichun Peter Liu ,  Shigehiro Asano ,  Anushkumar Rengarajan

IPC分类号： G06F12/08

CPC分类号： G06F12/0831 ,  G06F2212/1016

摘要： A system and method for using a data-only transfer protocol to store atomic cache line data in a local storage area is presented. A processing engine includes an atomic cache and a local storage. When the processing engine encounters a request to transfer cache line data from the atomic cache to the local storage (e.g., GETTLAR command), the processing engine utilizes a data-only transfer protocol to pass cache line data through the external bus node and back to the processing engine. The data-only transfer protocol comprises a data phase and does not include a prior command phase or snoop phase due to the fact that the processing engine communicates to the bus node instead of an entire computer system when the processing engine sends a data request to transfer data to itself.

摘要翻译： 提出了一种使用仅数据传输协议将原始高速缓存行数据存储在本地存储区域中的系统和方法。 处理引擎包括原子缓存和本地存储。 当处理引擎遇到将高速缓存行数据从原子缓存传送到本地存储器（例如，GETTLAR命令）的请求时，处理引擎利用仅数据传输协议通过外部总线节点传递高速缓存行数据并返回 处理引擎。 仅数据传输协议包括数据相位，并且不包括先前的命令阶段或窥探阶段，因为当处理引擎发送数据请求传送时处理引擎与总线节点而不是整个计算机系统通信 数据本身。

公开(公告)号：US06430687B1

公开(公告)日：2002-08-06

申请号：US09292192

申请日：1999-04-15

申请人： Maximino Aguilar ,  Norbert M. Blam ,  Michael Edward Criscolo ,  Sanjay Gupta ,  John William Gorrell, Jr. ,  Roy Moonseuk Kim ,  James Michael Stafford

发明人： Maximino Aguilar ,  Norbert M. Blam ,  Michael Edward Criscolo ,  Sanjay Gupta ,  John William Gorrell, Jr. ,  Roy Moonseuk Kim ,  James Michael Stafford

IPC分类号： G06F126

CPC分类号： G06F9/4416 ,  G06F11/1417

摘要： A computer network that includes a network server and a network client. The network server includes a storage medium configured with boot code data preferably comprising operating system software for the network client. The network client includes a power status indicator and is configured to query the power status indicator as part of a boot code sequence that is initiated in response to a boot event. The network client is configured to schedule retrieval of boot code data from the network server based upon the power status indicator. Preferably, the power status indicator includes a power fail circuit that indicates whether power to the network client has failed since a previous boot event. In one embodiment, the power fail circuit includes a flip flop arranged such that the output of the flip flop is preset when power is restored to the network client after a power failure. Preferably the clear input of the flip flop is programmably assertable. The power status indicator preferably further includes a power mode indicator that conveys information about the last known power mode of the network client. Preferably, the power mode indicator includes at least one nonvolatile memory bit.

摘要翻译： 包括网络服务器和网络客户端的计算机网络。 网络服务器包括配置有引导代码数据的存储介质，优选地包括用于网络客户端的操作系统软件。 网络客户端包括电源状态指示符，并且被配置为将电源状态指示符作为响应于引导事件而启动的引导代码序列的一部分进行查询。 网络客户端被配置为基于电源状态指示器来计划从网络服务器检索引导代码数据。 优选地，电源状态指示器包括电源故障电路，其指示对于网络客户端的电源是否从先前引导事件失败。 在一个实施例中，电源故障电路包括触发器，其被布置为使得在电源故障之后电力恢复到网络客户端时触发器的输出被预设。 优选地，触发器的清晰输入是可编程地可断言的。 电源状态指示符优选地还包括功率模式指示符，其传达关于网络客户端的最后已知功率模式的信息。 优选地，功率模式指示符包括至少一个非易失性存储器位。

公开(公告)号：US06691195B1

公开(公告)日：2004-02-10

申请号：US09519340

申请日：2000-03-06

申请人： Maximino Aguilar ,  Sanjay Gupta ,  Roy Moonseuk Kim ,  Yuan-Chang Lo ,  James Michael Stafford

发明人： Maximino Aguilar ,  Sanjay Gupta ,  Roy Moonseuk Kim ,  Yuan-Chang Lo ,  James Michael Stafford

IPC分类号： G06F1324

CPC分类号： G06F11/2733

摘要： A compact connector for a data processing system motherboard facilitates the performance of diagnostics on data processing system components. The connector includes first, second, and third terminals in communication with respective first, second, and third lines in the motherboard for serial port interrupts, system data, and keyboard interrupts, respectively. In an illustrative embodiment, the first and second lines comprise lines of an Industry Standard Architecture (ISA) bus, and the compact connector also includes a fourth terminal in communication with a fourth line in the motherboard for real-time-clock interrupts. This embodiment allows the motherboard to receive real-time-clock interrupts via the connector, so that a startup program of the data processing system may boot to an operating system that requires a real-time-clock. That operating system may then be utilized to test the motherboard. In addition, this embodiment allows one or more input devices in communication with the connector to be utilized to interact with the motherboard.

摘要翻译： 用于数据处理系统主板的紧凑型连接器有助于数据处理系统组件的诊断性能。 连接器包括与主板中的相应的第一，第二和第三线分别与串行端口中断，系统数据和键盘中断相通信的第一，第二和第三终端。 在说明性实施例中，第一和第二线包括工业标准架构（ISA）总线的线，并且紧凑连接器还包括与母板中的第四线通信的第四终端，用于实时时钟中断。 该实施例允许主板经由连接器接收实时时钟中断，使得数据处理系统的启动程序可以引导到需要实时时钟的操作系统。 然后可以使用该操作系统来测试主板。 此外，该实施例允许与连接器通信的一个或多个输入设备用于与主板交互。

公开(公告)号：US06067234A

公开(公告)日：2000-05-23

申请号：US995551

申请日：1997-12-22

申请人： Roy Moonseuk Kim ,  Sanjay Gupta

发明人： Roy Moonseuk Kim ,  Sanjay Gupta

IPC分类号： G06F1/18 ,  H05K1/14

CPC分类号： G06F1/183

摘要： An apparatus and method, for use with a data processing system having an architecture, which provide for the possibility of smart card use without unduly impacting the data processing system's architecture. An enclosure, having at least one PC card acceptor and at least one smart card acceptor, is created. A suspension mechanism is operably connected to enclosure in a fashion such that suspension mechanism is capable of physically connecting enclosure to a motherboard such that enclosure is suspended above a component of motherboard. The method and system give rise to several advantages. One advantage is that board space is saved in that the enclosure is suspended over existing board components. A second advantage is that the method and system allow original equipment manufactures to make the provision of smart card usage optional, in that smart card usage can be provided by a simple add-on to lower-end systems. A third advantage is the cost savings which comes from having integral PC card-smart card acceptors. A fourth advantage is that the method and system can be adapted to many configurations, such as providing alternate numbers of PC card and smart card acceptors, arranged in many different physical relationships. Those skilled in the art will recognize many other advantages in addition to those listed here.

摘要翻译： 一种用于具有架构的数据处理系统的装置和方法，其提供智能卡使用的可能性而不会不适当地影响数据处理系统的架构。 创建具有至少一个PC卡接收器和至少一个智能卡接收器的外壳。 悬挂机构可操作地连接到外壳，使得悬挂机构能够将外壳物理连接到主板，使得外壳悬挂在主板的部件上方。 该方法和系统产生了几个优点。 一个优点是可以节省电路板空间，因为机箱悬挂在现有的电路板组件上。 第二个优点是该方法和系统允许原始设备制造商提供可选的智能卡使用，因为智能卡使用可以通过简单的附加到低端系统来提供。 第三个优点是由具有集成PC卡智能卡接收器的成本节省。 第四个优点是该方法和系统可以适应许多配置，例如提供配置在许多不同物理关系中的备用数量的PC卡和智能卡接收器。 本领域技术人员除了这里列出的那些之外还将认识到许多其他优点。

公开(公告)号：US06799316B1

公开(公告)日：2004-09-28

申请号：US09534427

申请日：2000-03-23

申请人： Maximino Aguilar ,  Sanjay Gupta ,  Roy Moonseuk Kim ,  James Michael Stafford

发明人： Maximino Aguilar ,  Sanjay Gupta ,  Roy Moonseuk Kim ,  James Michael Stafford

IPC分类号： G06F9455

CPC分类号： G06F9/45537

摘要： Initially, a SMI trap detects an application accessing a memory location associated with a physical hardware device. The SMI trap receives the device address for the address bus and compares that address with memory addresses for hardware devices being virtualized by virtual device simulators. If the address matches an available virtual device, the SMI caches the address, hooks and caches the corresponding IO instruction for the memory address and issues a SMI. A SMI handler receives the SMI and determines which virtual device simulator to call. Once activated by the SMI handler, the virtual device simulator interacts with the application and then returns control to the processor.

摘要翻译： 最初，SMI陷阱检测到访问与物理硬件设备相关联的存储器位置的应用。 SMI陷阱接收地址总线的设备地址，并将该地址与由虚拟设备模拟器虚拟化的硬件设备的存储器地址进行比较。 如果地址与可用的虚拟设备匹配，则SMI会缓存地址，挂起并缓存相应的IO指令用于内存地址并发出SMI。 SMI处理程序接收SMI并确定要调用哪个虚拟设备模拟器。 一旦由SMI处理程序激活，虚拟设备模拟器将与应用程序交互，然后将控制权返回给处理器。

公开(公告)号：US06636918B1

公开(公告)日：2003-10-21

申请号：US09606638

申请日：2000-06-29

申请人： Maximino Aguilar ,  Sanjay Gupta ,  Roy Moonseuk Kim ,  James Michael Stafford

发明人： Maximino Aguilar ,  Sanjay Gupta ,  Roy Moonseuk Kim ,  James Michael Stafford

IPC分类号： G06F1300

CPC分类号： G06F1/1632

摘要： A mobile computing device and associated base stations are disclosed. The mobile computing device includes a system-on-chip (SOC) device that includes a general purpose processor core and a plurality of peripheral cells suitable for controlling a plurality of peripheral units. The mobile computing device further includes a system memory and a base unit interface. The base unit interface is suitable for connecting the mobile computing device to a base unit that includes a display adapter suitable for controlling a video display. The SOC is connected to and enabled to control the display adapter when the mobile computing device is connected to the base unit. The base unit interface may comprise a PCI interface that connects the SOC device to the base unit via a PCI bus. The plurality of peripheral units may include an audio adapter, a flash device, a wireless suitable for transmitting and receiving wireless information, and a liquid crystal display suitable for displaying text messages. The mobile device preferably further includes a battery suitable for powering the mobile computing device. The base unit suitably includes an interface configured to connect to the base unit interface of the mobile computing device and a display adapter enabled to control a display. The display adapter is connected to the interface unit via a peripheral bus that is connected to the SOC when the mobile computing device and the base unit are connected. The base unit may comprise a desktop base unit that includes a hard disk adapter, a CD ROM drive, a floppy diskette drive, a network device base unit that includes a network adapter, controlled by the SOC, that enables the base unit to communicate with a network server, or an internet appliance base unit that includes a modem controlled by the SOC and configured to enable the system to connect to the internet.

摘要翻译： 公开了移动计算设备和相关联的基站。 移动计算设备包括片上系统（SOC）设备，其包括通用处理器核和适于控制多个外围单元的多个外围单元。 移动计算设备还包括系统存储器和基本单元接口。 基本单元接口适用于将移动计算设备连接到包括适于控制视频显示器的显示适配器的基本单元。 当移动计算设备连接到基本单元时，SOC连接到并且能够控制显示适配器。 基本单元接口可以包括通过PCI总线将SOC设备连接到基本单元的PCI接口。 多个外围单元可以包括音频适配器，闪存设备，适用于发送和接收无线信息的无线电，以及适于显示文本消息的液晶显示器。 移动设备优选地还包括适于为移动计算设备供电的电池。 基本单元适当地包括被配置为连接到移动计算设备的基本单元接口的接口和能够控制显示器的显示适配器。 当移动计算设备和基站连接时，显示适配器经由连接到SOC的外围总线连接到接口单元。 基本单元可以包括桌面基本单元，其包括硬盘适配器，CD ROM驱动器，软盘驱动器，包括由SOC控制的网络适配器的网络设备基本单元，其使得基座单元能够与 网络服务器或互联网设备基本单元，其包括由SOC控制并被配置为使得系统能够连接到因特网的调制解调器。

公开(公告)号：US06473823B1

公开(公告)日：2002-10-29

申请号：US09323232

申请日：1999-06-01

申请人： Brian Michael Kerrigan ,  Roy Moonseuk Kim

发明人： Brian Michael Kerrigan ,  Roy Moonseuk Kim

IPC分类号： G06F1300

CPC分类号： G06F13/409

摘要： Components and circuitry, including a common microprocessor, are combined into a single motherboard that is common to both a Personal Computer (PC) and a Network Computer (NC). The motherboard is capable of receiving a riser card. Riser cards specific to either a NC or a PC are designed to provide functions that are not present on the common motherboard. Connector slots such as Integrated Drive Electronics (IDE), Industry Standard Architecture (ISA) and Peripheral Component Interconnect (PCI) are available on a PC riser card to accommodate additional circuit boards. Devices such as a hard drive, CD ROM drive, etc., may be installed utilizing appropriate connectors on a PC specific riser card that are not required or available on the NC. A riser card for the NC will accommodate a compact flash card connector or various other expansion cards that provide functions specific to the NC.

摘要翻译： 包括通用微处理器的组件和电路被组合成个人计算机（PC）和网络计算机（NC）共同的单个主板。 主板能够接收转接卡。 特定于NC或PC的提升卡被设计为提供在公共主板上不存在的功能。 连接器插槽，如集成驱动电子（IDE），工业标准架构（ISA）和外围组件互连（PCI）可用于PC转接卡，以适应其他电路板。 诸如硬盘驱动器，CD ROM驱动器等的设备可以利用在NC上不需要或可用的PC专用转接卡上的适当连接器来安装。 用于NC的转接卡可容纳紧凑型闪存卡连接器或提供特定于NC的功能的各种其他扩展卡。

公开(公告)号：US07353341B2

公开(公告)日：2008-04-01

申请号：US10860426

申请日：2004-06-03

申请人： Roy Moonseuk Kim ,  Yasukichi Okawa ,  Thuong Quang Truong

发明人： Roy Moonseuk Kim ,  Yasukichi Okawa ,  Thuong Quang Truong

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F12/127 ,  G06F12/0804 ,  G06F12/0831

摘要： A cache write back operation, write back modified data to memory from cache data array to fix inconsistency between them can be cancelled by the results of a comparison of the progress between a write back and snoop push or snoop kill operation. Write back is intended to make an empty slot to accommodate a reload data due to a cache miss and since a snoop push or snoop kill operation creates an invalid entry in the cache, write back is not needed. If simultaneous push or kill with write back operation exist, then write back machine is late cancelled. System performance improves due to preserving more cache lines in cache data array for possible future reuse.

摘要翻译： 缓存回写操作，将缓存数据数组中的修改后的数据写回到内存中以修复它们之间的不一致，可以通过比较回写和窥探推送或窥探杀手操作之间的进度的结果来取消缓存。 回写是为了使空槽容纳由于高速缓存未命中的重新加载数据，并且由于窥探推送或窥探杀手操作在高速缓存中创建无效条目，因此不需要回写。 如果同时推送或者杀死与回写操作存在，则回写机器被取消。 由于在缓存数据阵列中保留更多的高速缓存线，可能会再次使用系统性能。

公开(公告)号：US07089373B2

公开(公告)日：2006-08-08

申请号：US10460423

申请日：2003-06-12

申请人： Michael Norman Day ,  Roy Moonseuk Kim ,  Mark Richard Nutter ,  Yasukichi Okawa ,  Thuong Quang Truong

发明人： Michael Norman Day ,  Roy Moonseuk Kim ,  Mark Richard Nutter ,  Yasukichi Okawa ,  Thuong Quang Truong

IPC分类号： G06F12/00

CPC分类号： G06F9/526 ,  G06F9/3004 ,  G06F9/30087

摘要： A method and an apparatus are provided for enhancing lock acquisition in a multiprocessor system. A lock-load instruction is sent from a first processor to a cache. In response, a reservation flag for the first processor is set, and lock data is sent to the first processor. The lock data is placed in target and shadow registers of the first processor. Upon a determination that the lock is taken, the lock-load instruction is resent from the first processor to the cache. Upon a determination that the reservation flag is still set for the first processor, a status-quo signal is sent to the first processor without resending the lock data to the first processor. In response, the lock data is copied from the shadow register to the target register.

摘要翻译： 提供了一种用于增强多处理器系统中的锁获取的方法和装置。 锁定加载指令从第一处理器发送到高速缓存。 作为响应，设置第一处理器的预约标志，并将锁定数据发送到第一处理器。 锁定数据被放置在第一处理器的目标和影子寄存器中。 在确定锁定被采取后，锁定加载指令从第一处理器重新发送到高速缓存。 在确定对于第一处理器仍然设置了预留标志的情况下，将状态信号发送到第一处理器，而不将锁定数据重新发送到第一处理器。 作为响应，锁数据从影子寄存器复制到目标寄存器。

公开(公告)号：US06779110B1

公开(公告)日：2004-08-17

申请号：US09710923

申请日：2000-11-09

申请人： Maximino Aguilar ,  Sanjay Gupta ,  Roy Moonseuk Kim ,  James Michael Stafford

发明人： Maximino Aguilar ,  Sanjay Gupta ,  Roy Moonseuk Kim ,  James Michael Stafford

IPC分类号： G06F924

CPC分类号： G06F9/4416

摘要： A method and system for booting a user station in a computer network in which a first set of operating system information retrieved from the user station is used to attempt to boot the user station from a remote server. If the boot attempt fails, an iterative process is initiated in which a next set of operating system information is retrieved and used to attempt to boot the user station until a boot attempt is successful. Upon successfully booting the user station, the operating system information is modified to prioritize the set of information that resulted in a successful boot such that the successful set of information is selected first during a subsequent boot attempt. The operating system information may include a directory path of the remote server in which the user station attempts to locate an operating system kernel.

摘要翻译： 一种用于在计算机网络中引导用户站的方法和系统，其中使用从用户站检索的第一组操作系统信息来尝试从远程服务器引导用户站。 如果引导尝试失败，则启动迭代过程，在该过程中，检索下一组操作系统信息并将其用于尝试引导用户站，直到启动尝试成功。 在成功地引导用户站之后，修改操作系统信息来优先化导致成功启动的信息集，使得在随后的引导尝试期间首先选择成功的信息集。 操作系统信息可以包括用户站尝试定位操作系统内核的远程服务器的目录路径。