公开(公告)号：US09919913B2

公开(公告)日：2018-03-20

申请号：US14942824

申请日：2015-11-16

Applicant: Cirrus Logic, Inc.

Inventor： Shanjen Pan ,  Marc L. Tarabbia

IPC: B81C1/00 ,  H04R19/04 ,  B81B3/00 ,  H04R19/00

CPC classification number: B81B3/0086 ,  B81B2201/0257 ,  B81C1/00698 ,  H04R19/005 ,  H04R19/04 ,  H04R2307/025

Abstract: A fully depleted region may be used to reduce poly-to-substrate parasitic capacitance in an electronic device with poly-silicon layer. When the fully depleted region is located at least partially beneath the electronic device, an additional parasitic capacitance is formed between the fully depleted region and the substrate region. This additional parasitic capacitance is coupled in series with a first parasitic capacitance between a poly-silicon layer of the electronic device and the doped region. The series combination of the first parasitic capacitance and the additional parasitic capacitance results in an overall reduction of parasitic capacitance experience by an electronic device. The structure may include two doped regions on sides of the electronic device to form a fully depleted region based on lateral interaction of dopant in the doped regions and the substrate region.

公开(公告)号：US20160145093A1

公开(公告)日：2016-05-26

申请号：US14942824

申请日：2015-11-16

Applicant: Cirrus Logic, Inc.

Inventor： Shanjen Pan ,  Marc L. Tarabbia

IPC: B81B3/00 ,  B81C1/00 ,  H04R23/00

CPC classification number: B81B3/0086 ,  B81B2201/0257 ,  B81C1/00698 ,  H04R19/005 ,  H04R19/04 ,  H04R2307/025

Abstract: A fully depleted region may be used to reduce poly-to-substrate parasitic capacitance in an electronic device with poly-silicon layer. When the fully depleted region is located at least partially beneath the electronic device, an additional parasitic capacitance is formed between the fully depleted region and the substrate region. This additional parasitic capacitance is coupled in series with a first parasitic capacitance between a poly-silicon layer of the electronic device and the doped region. The series combination of the first parasitic capacitance and the additional parasitic capacitance results in an overall reduction of parasitic capacitance experience by an electronic device. The structure may include two doped regions on sides of the electronic device to form a fully depleted region based on lateral interaction of dopant in the doped regions and the substrate region.

Abstract translation: 可以使用完全耗尽区域来减少具有多晶硅层的电子器件中的多对衬底寄生电容。 当完全耗尽区域至少部分地位于电子器件下方时，在完全耗尽区域和衬底区域之间形成附加的寄生电容。 该额外的寄生电容与电子器件的多晶硅层与掺杂区域之间的第一寄生电容串联耦合。 第一寄生电容和附加寄生电容的串联组合导致电子器件的寄生电容体验的总体减小。 该结构可以在电子器件的侧面上包括两个掺杂区域，以基于掺杂区域和衬底区域中掺杂剂的横向相互作用形成完全耗尽区域。

公开(公告)号：US20180190648A1

公开(公告)日：2018-07-05

申请号：US15910843

申请日：2018-03-02

Applicant: Cirrus Logic, Inc.

Inventor： Zhonghai Shi ,  Marc L. Tarabbia

IPC: H01L27/06 ,  H01L21/8234 ,  H01L27/08 ,  H01L29/78 ,  H01L29/66 ,  H01L49/02

CPC classification number: H01L27/0629 ,  H01L21/823431 ,  H01L27/0805 ,  H01L28/86 ,  H01L28/90 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A vertical structure may be used as a high density capacitance for an integrated circuit. These thin vertical structures can be configured to operate as an insulator in a metal-insulator-metal (MIM) capacitor. The vertical structures may be manufactured using three-dimensional semiconductor manufacturing technology, such as FinFET (fin field effect transistor) technology and manufacturing processes. The capacitors based on thin vertical structures may be integrated with other circuitry that can utilize the thin vertical structures, such as FinFET transistors.

公开(公告)号：US09275992B1

公开(公告)日：2016-03-01

申请号：US14559602

申请日：2014-12-03

Applicant: Cirrus Logic, Inc.

Inventor： Marc L. Tarabbia ,  Shanjen Pan

IPC: H01L21/00 ,  H01L27/06 ,  H01L49/02

CPC classification number: H01L27/0682 ,  H01L28/20 ,  H01L28/40

Abstract: Trenches may be formed in layers on a semiconductor substrate for defining electrical components for an electronic device, such as an amplifier. A polishing step may be performed after formation of the trenches and deposition of other layer(s) to define regions for resistors, capacitors, or other elements in a metal layer on a semiconductor substrate. The polishing step may create discontinuities in metal layers on the semiconductor substrate that define electrically isolated regions corresponding to the resistors, capacitor, and other components of the electronic device.

Abstract translation: 沟槽可以形成在半导体衬底上的层中，用于限定诸如放大器之类的电子器件的电气部件。 可以在形成沟槽和沉积其它层以在半导体衬底上的金属层中限定电阻器，电容器或其它元件的区域之后进行抛光步骤。 抛光步骤可能在半导体衬底上的金属层中产生不连续性，其限定对应于电子器件的电阻器，电容器和其它部件的电隔离区域。