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公开(公告)号：US20210033654A1
公开(公告)日：2021-02-04
申请号：US16530606
申请日：2019-08-02
Inventor： Cory Jay Peterson , Chandra B. Prakash , Anand Ilango , Ramin Zanbaghi , Dejun Wang
Abstract: A detector for measuring a resistance of a variable resistance sensor (VRS) that varies with respect to a time-varying stimulus (e.g., temperature) includes a voltage reference having variation with respect to operating conditions and a linearized digital-to-analog converter (LIDAC) having a known transconductance that uses the voltage reference to generate a current for pumping into the VRS to cause the VRS to generate a voltage sensed by the detector. The sensed voltage includes error due to the variation of the voltage reference. The detector also includes a programmable gain amplifier (PGA) that gains up the sensed voltage to generate an output signal, an ADC that converts the output signal to a digital value, and a digital processor that computes the resistance of the VRS using the digital value and the known transconductance. The PGA is non-varying with respect to the time-varying stimulus.
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公开(公告)号：US11644493B2
公开(公告)日：2023-05-09
申请号：US17668445
申请日：2022-02-10
Inventor： Saurabh Singh , Chandra B. Prakash , Eric Kimball , Cory J. Peterson , Ryan Lobo
CPC classification number: G01R27/08 , G01R17/105 , G01R27/02 , G01R19/0084 , G01R19/0092
Abstract: A method for estimating resistances of a circuit having a plurality of resistances comprising a first resistance and a second resistance may include applying a first bias voltage across the circuit and measuring a first voltage at a common node between the first resistance and the second resistance in order to determine a mathematical relationship between the first resistance and the second resistance, applying a second bias voltage across the circuit and a third resistance in parallel with the circuit and measuring a second voltage at the common node between the first resistance and the second resistance in order to determine a mathematical relationship between the third resistance and at least one of the first resistance and the second resistance, and based on at least the measurement of the first voltage and the measurement of the second voltage, determining the first resistance and the second resistance as a function of the third resistance.
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公开(公告)号：US10826512B1
公开(公告)日：2020-11-03
申请号：US16530618
申请日：2019-08-02
Inventor： Cory Jay Peterson , Chandra B. Prakash , Anand Ilango , Ramin Zanbaghi , Dejun Wang
Abstract: A system includes a first sensed voltage generated as a product of the first voltage reference and an unknown scalar, a second sensed voltage generated as a product of the first voltage reference and a known scalar, and an amplifier having gain error that generates a second voltage reference (first voltage reference or scaled version thereof). An ADC uses the second voltage reference to generate first and second digital values, representing the first and second sensed voltages, that contain error caused by the second voltage reference gain error. A processor uses the known scalar and a ratio based on the first and second digital values to remove the error from the first digital value. The first sensed voltage may be generated by pumping a current into a variable resistance sensor (VRS) whose resistance varies with respect to a time-varying stimulus (e.g., temperature) and is proportional to the unknown scalar.
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公开(公告)号：US11979115B2
公开(公告)日：2024-05-07
申请号：US17739480
申请日：2022-05-09
Inventor： Siddharth Maru , Chandra B. Prakash , Tejasvi Das
CPC classification number: H03F3/04 , B06B1/0207 , H03F2200/129 , H03F2200/481
Abstract: An amplifier system may include a first feedback loop coupled between an output of an amplifier to an input of a modulator for regulating an output voltage driven at the output of the amplifier to a first terminal of a load of the amplifier system, a sense resistor for sensing a physical quantity associated with the amplifier, a second control loop coupled to the sense resistor such that the sense resistor is outside of the second control loop, the second control loop configured to regulate a common-mode voltage at a second terminal of the load, and a common-mode feedforward circuit coupled to the sense resistor and configured to minimize effects of a signal-dependent common-mode feedback of the sense resistor.
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Patent Agency Ranking
公开(公告)号：US11644494B1
公开(公告)日：2023-05-09
申请号：US17690402
申请日：2022-03-09
Inventor： Chandra B. Prakash , Tejasvi Das , Siddharth Maru
Abstract: Circuitry for driving a load, the circuitry comprising: driver circuitry; load sensing circuitry; and a parameter estimation engine, wherein the circuitry is operable in: a driving mode of operation in which the driver circuitry supplies a drive signal to a load coupled to the circuitry; and a load sensing mode of operation, for estimating a characteristic of a load coupled to the circuitry based on a signal output by the load sensing circuitry in response to a stimulus signal supplied to the driver circuitry, and wherein the circuitry is operable to perform a calibration operation in which the parameter estimation engine generates a circuit parameter for use in the load sensing mode based, at least in part, on a signal generated by the circuitry in response to a calibration stimulus signal supplied to the driver circuitry.
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公开(公告)号：US11119134B2
公开(公告)日：2021-09-14
申请号：US16530606
申请日：2019-08-02
Inventor： Cory Jay Peterson , Chandra B. Prakash , Anand Ilango , Ramin Zanbaghi , Dejun Wang
Abstract: A detector for measuring a resistance of a variable resistance sensor (VRS) that varies with respect to a time-varying stimulus (e.g., temperature) includes a voltage reference having variation with respect to operating conditions and a linearized digital-to-analog converter (LIDAC) having a known transconductance that uses the voltage reference to generate a current for pumping into the VRS to cause the VRS to generate a voltage sensed by the detector. The sensed voltage includes error due to the variation of the voltage reference. The detector also includes a programmable gain amplifier (PGA) that gains up the sensed voltage to generate an output signal, an ADC that converts the output signal to a digital value, and a digital processor that computes the resistance of the VRS using the digital value and the known transconductance. The PGA is non-varying with respect to the time-varying stimulus.
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公开(公告)号：US12176057B2
公开(公告)日：2024-12-24
申请号：US17545378
申请日：2021-12-08
Inventor： Chandra B. Prakash , Cory J. Peterson
IPC: G11C7/10 , H03K19/003
Abstract: In accordance with embodiments of the present disclosure, a system may include a driver configured to drive a load with a single-ended driving signal and a signal return path for the load, wherein the signal return path comprises a voltage-mode driver configured to create a signal offset during an idle channel mode of the system in order to minimize idle channel noise at the load.
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公开(公告)号：US11854738B2
公开(公告)日：2023-12-26
申请号：US17540648
申请日：2021-12-02
Inventor： Chandra B. Prakash , Ramin Zanbaghi
CPC classification number: H01F7/064 , H02K33/00 , H04R9/06 , H04R2400/03
Abstract: A system may include an electromagnetic load, a driver configured to drive the electromagnetic load with a driving signal, and a processing system communicatively coupled to the electromagnetic load and configured to, during a haptic mode of the system couple a first terminal of the electromagnetic load to a ground voltage and cause the driving signal to have a first slew rate, and during a load sensing mode of the system for sensing a current associated with the electromagnetic load, couple the first terminal to a current-sensing circuit having a sense resistor coupled between the first terminal and an electrical node driven to a common-mode voltage and cause the driving signal to have a second slew rate lower than the first slew rate.
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公开(公告)号：US11799428B2
公开(公告)日：2023-10-24
申请号：US17573000
申请日：2022-01-11
Inventor： Saurabh Singh , Chandra B. Prakash
CPC classification number: H03F3/04 , G01D18/00 , H03F2200/375
Abstract: A method may include receiving, by a calibration circuit, an output of a subsystem comprising the sensor and the analog front end. The method may further include separating the output individually into the sensor offset and the amplifier offset by using inherent properties of separate frequency ranges for the sensor offset and the amplifier offset. The method may also include calibrating, by the calibration circuit, the sensor offset by determining a first calibration value for the sensor offset such that the output approximates zero during an idle-channel condition. The method may additionally include calibrating, by the calibration circuit, the amplifier offset by determining a second calibration value for the amplifier offset such that the output approximates zero during the idle-channel condition.
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