公开(公告)号：US12101097B2

公开(公告)日：2024-09-24

申请号：US17987448

申请日：2022-11-15

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Paul Wilson ,  James T. Deas ,  Mucahit Kozak ,  Graeme G. Mackay

IPC: H03M1/10 ,  H03M1/06

CPC classification number: H03M1/1023 ,  H03M1/0609

Abstract: Coulomb counter circuitry operable in a first mode of operation and a second mode of operation, the coulomb counter circuitry comprising: first analog to digital converter (ADC) circuitry configured to generate a first ADC output signal indicative of a current through a load coupled to the coulomb counter circuitry; second analog to digital converter (ADC) circuitry; offset correction circuitry; and accumulator circuitry configured to generate a signal indicative of a cumulative amount of charge transferred to the load, wherein in the second mode of operation, the coulomb counter circuitry is operable to enable the second ADC circuitry and to generate an offset correction factor based at least in part on a second ADC output signal output by the second ADC circuitry, and wherein in subsequent operation of the coulomb counter circuitry in the first mode of operation, the offset correction circuitry applies the offset correction factor to the first ADC output signal.

公开(公告)号：US11777516B2

公开(公告)日：2023-10-03

申请号：US17667953

申请日：2022-02-09

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： John L. Melanson ,  Axel Thomsen ,  Mucahit Kozak ,  Paul Wilson ,  Eric J. King

IPC: H03M3/00

CPC classification number: H03M3/344 ,  H03M3/422

Abstract: A signal processing system may include a sensor readout channel configured to convert an electronic signal into a digital quantity. The sensor readout channel may include a first-order sigma-delta modulator having a modulator input and a modulator output, first outside chopping switches located at the modulator input, second outside chopping switches located at the modulator output, an auxiliary path having an analog-to-digital converter (ADC) having an auxiliary path input and an auxiliary path output, the auxiliary path input configured to receive as its input signal a signal output by a memory element of the first-order sigma-delta modulator, and a signal combiner configured to combine a modulator output signal generated by the first-order sigma-delta modulator with an auxiliary path output signal generated by the auxiliary path to generate a combined output signal.