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公开(公告)号：US20240275399A1
公开(公告)日：2024-08-15
申请号：US18436340
申请日：2024-02-08
Applicant: SKYWORKS SOLUTIONS, INC.
Inventor： Abhishek Bandyopadhyay , Barkat A. Wani
IPC: H03M3/00
Abstract: There is a presented a system for setting a noise transfer function comprising an input configured to receive an analog signal; a quantizer configured to quantize the analog signal to produce a digital signal; a preamplifier configured to adjust at least the amplitude the analog signal; and a resonator configured to adjust at least the amplitude of the analog signal, an output of the resonator being coupled to an output of the preamplifier, the system providing greater attenuation to the analog signal in a frequency band determined by the preamplifier and the resonator.
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公开(公告)号：US12021541B2
公开(公告)日：2024-06-25
申请号：US18129527
申请日：2023-03-31
Applicant: SIGMASENSE, LLC.
Inventor： Phuong Huynh
CPC classification number: H03M1/004 , H03M1/0626 , H03M1/0854 , H03M1/1245 , H03M1/34 , H03M3/462 , H03M3/476 , H03M3/422
Abstract: A high resolution analog to digital converter (ADC) with improved bandwidth senses an analog signal (e.g., a load current) to generate a digital signal. The ADC operates based on a load voltage produced based on charging of an element (e.g., a capacitor) by a load current and a digital to analog converter (DAC) output current (e.g., from a N-bit DAC). The ADC generates a digital output signal representative of a difference between the load voltage and a reference voltage. This digital output signal is used directly, or after digital signal processing, to operate an N-bit DAC to generate a DAC output current that tracks the load current. In addition, quantization noise is subtracted from the digital output signal thereby extending the operational bandwidth of the ADC. In certain examples, the operational bandwidth of the ADC extends up to 100s of kHz (e.g., 200-300 kHz), or even higher.
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公开(公告)号：US20240187019A1
公开(公告)日：2024-06-06
申请号：US18494541
申请日：2023-10-25
Applicant: Beyond Semiconductor, d.o.o.
Inventor： Matjaz Breskvar , Drago Strle
IPC: H03M3/00
Abstract: Systems and methods provide architectures for various applications, for example, for software defined radios and other high frequency (HF) application. Embodiments can provide novel multi path ΣΔ architectures that form the basis for novel N path Sigma Delta (NΣΔ) modulators, NΣΔ digital to analog converters (NΣΔ DAC) and NΣΔ analog to digital converters (NΣΔ ADC).
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公开(公告)号：US20240063812A1
公开(公告)日：2024-02-22
申请号：US17820975
申请日：2022-08-19
Applicant: Infineon Technologies AG
Inventor： Ahmed Abdelaal , John G. Kauffman , Maurits Ortmanns , Takashi Miki
IPC: H03M3/00
Abstract: In accordance with an embodiment, a delta-sigma modulator includes: an analog loop filter comprising an outer portion and an inner portion having an input coupled to the outer portion; a quantizer coupled to an output of the inner portion of the analog loop filter; an outer feedback path coupled between an output of the quantizer and an input to the outer portion of the analog loop filter; and a compensation filter coupled between an output of the quantizer and an input of the inner portion of the analog loop filter. The compensation filter has a transfer function configured to correct for an effect of excess loop delay (ELD) on the delta-sigma modulator.
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公开(公告)号：US11777517B2
公开(公告)日：2023-10-03
申请号：US17096582
申请日：2020-11-12
Inventor： Chandra Prakash , Bhupendra Manola , John L. Melanson
IPC: H03M3/00
Abstract: An integrated circuit having multiple switched-capacitor delta-sigma data converter circuits includes compensation for voltage reference error due to leakage current that causes reference voltage droop. The reference filter capacitor terminal voltage is maintained by periodic connection to the reference feedback capacitor(s) that are alternately connected to a voltage reference buffer, and the leakage into the reference feedback capacitor networks of disabled converter circuits causes reference voltage droop. The compensation is either determined from the number of converter circuits that are disabled, or from an error between the filter capacitor voltage and a separate voltage reference, and may be applied by adjusting a resistance selectively coupled between the voltage reference buffer output and the filter capacitor, feedback applied to the voltage reference buffer or its input source. Alternatively, or in combination, correction may be applied to the output of the active converters by digital adjustment of output values.
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Patent Agency Ranking
公开(公告)号：US11777516B2
公开(公告)日：2023-10-03
申请号：US17667953
申请日：2022-02-09
Inventor： John L. Melanson , Axel Thomsen , Mucahit Kozak , Paul Wilson , Eric J. King
IPC: H03M3/00
Abstract: A signal processing system may include a sensor readout channel configured to convert an electronic signal into a digital quantity. The sensor readout channel may include a first-order sigma-delta modulator having a modulator input and a modulator output, first outside chopping switches located at the modulator input, second outside chopping switches located at the modulator output, an auxiliary path having an analog-to-digital converter (ADC) having an auxiliary path input and an auxiliary path output, the auxiliary path input configured to receive as its input signal a signal output by a memory element of the first-order sigma-delta modulator, and a signal combiner configured to combine a modulator output signal generated by the first-order sigma-delta modulator with an auxiliary path output signal generated by the auxiliary path to generate a combined output signal.
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公开(公告)号：US20230308111A1
公开(公告)日：2023-09-28
申请号：US17701742
申请日：2022-03-23
Applicant: Silicon Laboratories Inc.
Inventor： John M. Khoury
CPC classification number: H03M3/422 , H03M3/356 , H03M3/458 , H03F3/183 , H04R3/04 , H04R3/02 , H03F2200/03
Abstract: In one embodiment, an analog-to-digital converter includes: a sum circuit to receive an analog input signal and a feedback reference signal and generate a sum signal; a feedback circuit coupled to the sum circuit to provide the feedback reference signal to the sum circuit; a filter coupled to the sum circuit to receive the sum signal and generate a filtered signal; and a punctured quantizer coupled to the filter to receive the filtered signal and quantize the filtered signal to a digital output and to output the digital output and to provide the digital output to the feedback circuit.
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公开(公告)号：US09985645B2
公开(公告)日：2018-05-29
申请号：US15652252
申请日：2017-07-18
Applicant: MEDIATEK INC.
Inventor： Pao-Cheng Chiu , Hung-Yi Hsieh
IPC: H03M3/00
Abstract: A delta-sigma modulator includes a receiving circuit, a loop filter, a quantizer, a dynamic element matching circuit and a digital to analog converter. The receiving circuit is arranged for receiving a feedback signal and an input signal to generate a summation signal. The loop filter is arranged for receiving the summation signal to generate a filtered summation signal. The quantizer is arranged for generating a digital output signal according to the filtered summation signal. The dynamic element matching circuit is arranged for receiving the digital output signal to generate a shaped digital output signal for shaping element mismatch. The digital to analog converter is arranged for performing a digital to analog converting operation upon a signal derived from the shaped digital output signal to generate the feedback signal to the receiving circuit, wherein clock signals used by the quantizer and the dynamic element matching circuit have different frequencies.
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9.发明申请公开(公告)号：US20180048327A1
公开(公告)日：2018-02-15
申请号：US15554970
申请日：2015-04-01
Applicant: TDK Corporation
Inventor： Niels Marker-Villumsen
IPC: H03M3/00
Abstract: A sigma-delta modulator arrangement includes a continuous-time sigma-delta modulator with at least one modulator stage, a digital integrator and a given number of switches. The switches are arranged and configured to convert the continuous-time sigma-delta modulator into a first order incremental sigma-delta analog-to-digital converter comprising the digital integrator. At least a first modulator stage of the continuous-time sigma-delta-modulator, which is coupled with an input of the continuous-time sigma-delta modulator, includes at least one tuning element for adjusting an input signal and/or a feedback signal which are supplied to the first modulator stage.
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10.发明申请公开(公告)号：US20170359078A1
公开(公告)日：2017-12-14
申请号：US15687414
申请日：2017-08-25
Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Inventor： Alexander HEUBI
CPC classification number: H03M1/08 , H03F3/45475 , H03F2200/03 , H03F2200/264 , H03F2203/45288 , H03M1/00 , H03M1/12 , H03M3/422 , H03M3/464 , H03M3/50 , H04R3/02
Abstract: A system to convert between analog and digital signals, in some embodiments, comprises: a differentiator to produce a differentiated signal based on an input signal and a feedback signal; an integrator, coupled to the differentiator, to integrate the differentiated signal; a quantizer, coupled to the integrator, to quantize the integrated signal; and a low-pass feedback filter, coupled between an output of the quantizer and an input of the differentiator, to generate said feedback signal using the quantized signal, wherein the low-pass feedback filter pushes at least some noise of the quantized signal downward in the frequency spectrum.
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