公开(公告)号：US11119524B1

公开(公告)日：2021-09-14

申请号：US16815505

申请日：2020-03-11

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Christopher M. Dougherty ,  Anindya Bhattacharya ,  Vaibhav Pandey ,  Ying Ou

IPC: G05F3/26

Abstract: A selectable output current mirror may include a reference leg configured to generate a reference current, an output leg electrically coupled to the reference leg in a manner such that the output leg is configured to generate at an output of the output leg an output current proportional to the reference current, wherein the output leg comprises an output leg transistor, a drain path switch coupled between a first non-gate terminal of the output leg transistor and the output of the output leg, and a series combination of a degeneration resistor and a degeneration path switch coupled between a second non-gate terminal of the output leg transistor and a voltage source to the selectable output current mirror. The selectable output current mirror may also include switch control circuitry configured to selectively enable and disable the output leg from generating the output current by selectively enabling and disabling the drain path switch and the degeneration path switch and glitch mitigation circuitry coupled to the second non-gate terminal of the output leg transistor and configured to maintain the second non-gate terminal of the output leg transistor at a substantially-constant voltage during transitions between disabling of the degeneration path switch and enabling of the degeneration path switch.

公开(公告)号：US11082012B2

公开(公告)日：2021-08-03

申请号：US16409580

申请日：2019-05-10

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Vaibhav Pandey ,  Bhoodev Kumar

IPC: H03F3/45 ,  H03F1/32 ,  H03F1/56 ,  H03M1/66

Abstract: An amplifier includes input transconductors that receive an input signal, the input signal having a voltage swing. A supply side current mirror generates a gate voltage as a function of input signal voltage and current sources that provide a bias current of the input transconductors as a function of the gate voltage to maintain a constant bias current across the voltage swing of the input signal. Resistors average source voltages of the transconductance-cancelling transconductors to provide an average source voltage and apply the average source voltage to wells of input devices of the transconductance-cancelling transconductors to reduce back bias effect. The input devices are laid out in a same well and have a common centroid to cancel out process mismatches. A first I-DAC trims an offset of first transconductors, and a second I-DAC trims an offset of second transconductors to attain low offsets across a rail-to-rail input common mode range.

公开(公告)号：US20170163252A1

公开(公告)日：2017-06-08

申请号：US14962615

申请日：2015-12-08

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Vaibhav Pandey ,  John L. Melanson ,  Anindya Bhattacharya

IPC: H03K5/24 ,  H03K3/3565

CPC classification number: H03K5/2481 ,  H03K3/02337 ,  H03K3/3565

Abstract: In accordance with embodiments of the present disclosure, a comparator may include a transconductance stage having an input configured to receive an input voltage and generate an intermediate current responsive to the input voltage, a hysteretic current source configured to generate a hysteretic current, an output stage configured to generate an output signal based at least on the intermediate current, and a switch responsive to the output stage and configured to combine the intermediate current and the hysteretic current to generate a combined current, such that the output stage generates the output signal based at least on the intermediate current and the hysteretic current when output signal has a first value.