公开(公告)号：US07502342B2

公开(公告)日：2009-03-10

申请号：US10778240

申请日：2004-02-17

申请人： Dae-ung Kim ,  Na-yeon Kim

发明人： Dae-ung Kim ,  Na-yeon Kim

IPC分类号： H04B7/212

CPC分类号： H04W56/001 ,  H04J3/0641 ,  H04W84/18

摘要： A resynchronization method for wireless ad-hoc network environments that are synchronized by a synchronization signal broadcast from one arbiter includes (a) preparing a candidate arbiters list that lists the wireless access devices linked to a wireless ad-hoc network that are capable of becoming candidate arbiters; (b) sending the candidate arbiters list to the wireless access devices of the wireless ad-hoc network; and (c) broadcasting the synchronization signal by a wireless access device selected as a new arbiter based on the candidate arbiters list, if the synchronization signal is not broadcast for a predetermined timeout period. Accordingly, if an arbiter stops its operations in the wireless ad-hoc network, the resynchronization is rapidly performed by the most suitable wireless access device.

摘要翻译： 用于通过从一个仲裁器广播的同步信号同步的无线自组织网络环境的再同步方法包括（a）准备列出能够成为候选者的无线ad-hoc网络链接的无线接入设备的候选仲裁器列表 仲裁者 （b）将候选仲裁者列表发送到无线自组织网络的无线接入设备; 以及（c）如果同步信号在预定的超时时段内未被广播，则通过基于候选仲裁器列表选择为新的仲裁器的无线接入设备来广播同步信号。 因此，如果仲裁者在无线自组织网络中停止其操作，则最适合的无线接入设备快速执行重新同步。

公开(公告)号：US20060095733A1

公开(公告)日：2006-05-04

申请号：US11219797

申请日：2005-09-07

申请人： Yong-surk Lee ,  Ha-young Jeong ,  Nam-guk Kim ,  Jin-oo Joung ,  Tae-ho Jang ,  Dae-ung Kim

发明人： Yong-surk Lee ,  Ha-young Jeong ,  Nam-guk Kim ,  Jin-oo Joung ,  Tae-ho Jang ,  Dae-ung Kim

IPC分类号： G06F9/30

CPC分类号： G06F9/30072

摘要： A hardware device for executing conditional instructions out-of-order and the execution method. An architecture is provided, enabling the hardware device such as a processor supporting the conditional instruction and a computer system to execute the instruction out-of-order. To this end, a conditional execution buffer is provided, and a register of a destination operand of the conditional instruction is renamed to another register. Hence, the hardware device using the conditional instruction can carry out the out-of-order execution, and the execution speed of the hardware device can be greatly improved.

摘要翻译： 用于执行无序条件指令和执行方法的硬件设备。 提供了一种架构，使诸如支持条件指令的处理器等硬件设备和计算机系统执行无序指令。 为此，提供了条件执行缓冲器，并将条件指令的目的地操作数的寄存器重命名为另一个寄存器。 因此，使用条件指令的硬件设备可以执行无序执行，并且可以大大提高硬件设备的执行速度。