CONTROL SYSTEM AND CONTROL DEVICE
    1.
    发明公开

    公开(公告)号:US20240275511A1

    公开(公告)日:2024-08-15

    申请号:US18490836

    申请日:2023-10-20

    IPC分类号: H04J3/06

    CPC分类号: H04J3/0641 H04J3/0658

    摘要: According to one embodiment, a control system includes first and second control devices. The first control device includes a management unit that manages global time, a first generation unit that generates local time, a control unit that controls an operation of the first control device based on the global time, the local time, and operation control information, and a second generation unit that generates time error information based on the global time and the local time. The second control device includes an acquisition unit that acquires the time error information, and a correction unit that corrects the operation control information based on the time error information.

    NETWORK SWITCH AND CIRCUIT BOARD WHERE PRECISION TIME PROTOCOL MODULE IS USED

    公开(公告)号:US20230171016A1

    公开(公告)日:2023-06-01

    申请号:US17993986

    申请日:2022-11-24

    发明人: Kuan-Tse Lee

    IPC分类号: H04J3/06

    CPC分类号: H04J3/0667 H04J3/0641

    摘要: A network switch can include a precision time protocol (PTP) module and a circuit board. The PTP module can provide a first clock signal and include a predetermined interface. The circuit board can include a socket, an oscillator and a selection unit. The socket can be inserted by the predetermined interface to receive the first clock signal. The oscillator can provide a second clock signal. The selection unit can include a first terminal, a second terminal, an output terminal and a selection terminal. The first terminal can receive the first clock signal when the predetermined interface is inserted into the socket. The second terminal can receive the second clock signal. The output terminal can output one of the first clock signal and the second clock signal. The selection terminal can receive a selection signal to control the output terminal to output the first clock signal or the second clock signal.

    TIME SYNCHRONIZATION PACKET PROCESSING METHOD AND DEVICE

    公开(公告)号:US20180262287A1

    公开(公告)日:2018-09-13

    申请号:US15760870

    申请日:2016-09-05

    发明人: Liuyan HAN Han LI

    IPC分类号: H04J3/06

    摘要: Provided are a time synchronization packet processing method and device, which are applied to a time synchronization node. The processing method comprises: according to a change condition of received time source information, judging whether a time synchronization node tracking time source changes; and when the time synchronization node tracking time source changes, and after a predetermined time delay, sending to a downstream clock node a time synchronization packet parameter modified according to the change condition of the time source information. By distinguishing a change condition of time source information input by a time synchronization node, and when the change condition of the time source information changes a time synchronization node tracking time source, setting a certain delay time for changing and outputting a time synchronization packet parameter, the present invention avoids unnecessary downstream oscillation, and ensures the stable operation of a time synchronization network.

    Fault tolerant clock network
    6.
    发明授权

    公开(公告)号:US09973601B2

    公开(公告)日:2018-05-15

    申请号:US14198351

    申请日:2014-03-05

    IPC分类号: G06F15/16 H04L29/06 H04J3/06

    摘要: Fault tolerant and redundant grand master clock scheme may reduce or eliminate precision time transition caused by a network link or device failure. A primary synchronization message may be sent by a primary grandmaster clock and one or more backup synchronization message may be sent by respective backup grandmaster clocks. The primary and backup grandmaster clocks may be concurrently operated. The primary and backup synchronization messages may be sent to an end station over a network. The end station may derive a local clock based on one, some, or all of the received messages. The end station may or may not distinguish between the messages based on the clock source. The end station may validate messages received from a particular clock source.

    Simplified synchronized Ethernet implementation

    公开(公告)号:US09887794B2

    公开(公告)日:2018-02-06

    申请号:US15431043

    申请日:2017-02-13

    IPC分类号: H04J3/06

    摘要: A method of simplifying the implementation of Synchronous Ethernet on an Ethernet device having a first port and a second port device using a predetermined protocol and signaling, comprises delivering a master clock from a Synchronous Ethernet system to the first port of the Ethernet device; transmitting the delivered master clock to the second port of the Ethernet device independently of the protocol and signaling of the Ethernet device; and transmitting the master clock from the second port of the Ethernet device to a downstream device that supports Synchronous Ethernet. In one implementation, the Ethernet device has a local clock, and the method synchronizes the local clock to the master clock. In another implementation, the Ethernet device does not have a local clock, and the master clock is transmitted from the second port of the Ethernet device to the downstream device without any synchronizing operation at the Ethernet device.