公开(公告)号：US5764300A

公开(公告)日：1998-06-09

申请号：US504802

申请日：1995-07-20

申请人： David Mark Badger

发明人： David Mark Badger

IPC分类号： H04N5/44 ,  H03L7/093 ,  H03L7/10 ,  H03L7/107 ,  H04N5/50

CPC分类号： H03L7/10 ,  H03L7/107

摘要： A more rapid charging of an integrating capacitor of a PLL is provided when large frequency changes are desired. In one embodiment, the phase locked loop (PLL) circuit sinks or sources current to charge or discharge the integrating capacitor. A threshold voltage proportional to a current through the capacitor turns on a circuit which sinks or sources more current of the proper polarity to the integrating capacitor from an external source until a PLL lock is achieved. Once the lock is achieved, if a small correction current is required by the PLL, the small correction current is below a threshold required to actuate the augmenting circuit, and the PLL loop behaves in the usual manner as if the augmenting circuit were not present. In another embodiment, the integrating capacitor is reduced in value by switchably connecting a second capacitor in series with the integrating capacitor so that the total reduced capacitance of reduced value can be charged more quickly.

摘要翻译： 当需要大的频率变化时，提供PLL的积分电容器的更快速的充电。 在一个实施例中，锁相环（PLL）电路吸收或输出电流以对积分电容器进行充电或放电。 与通过电容器的电流成比例的阈值电压使来自外部源的积分电容器的正常极性的更多电流吸收或者获得更多的电流，直到达到PLL锁定为止。 一旦实现锁定，如果PLL需要小的校正电流，则小的校正电流低于启动增加电路所需的阈值，并且PLL环路以通常的方式表现为如同不存在增强电路。 在另一个实施例中，积分电容器的值通过可逆地连接与积分电容器串联的第二电容器来降低，从而能够更快地充电降低的总电容。

公开(公告)号：US5748046A

公开(公告)日：1998-05-05

申请号：US882129

申请日：1997-06-25

申请人： David Mark Badger

发明人： David Mark Badger

IPC分类号： H03L7/093 ,  H03J1/00 ,  H03J5/02 ,  H03L7/107 ,  H04L27/00 ,  H04L27/233

CPC分类号： H03L7/107 ,  H03J1/005 ,  H04L27/2332 ,  H03L7/093 ,  H04L2027/0032 ,  H04L2027/0055 ,  H04L2027/0057 ,  H04L2027/0067 ,  H04L2027/0069

摘要： An arrangement for selectively controlling the response time of a type II phase locked loop (PLL), especially one which includes a phase detector and an amplifier of a feedback type of integrator within an IC, comprises a controllable filter stage coupled in cascade with the amplifier. The controllable filter stage includes a filter section and a switching arrangement for selectively bypassing the filter section in response to a mode -determining control signal. In the described embodiment, the PLL controls the frequency of a local oscillator of a tuner and the second filter section has an amplitude versus frequency response for increasing the response time of the PLL during a fine tuning mode so that a demodulator can continue to operate properly during the fine tuning mode.

摘要翻译： 用于选择性地控制II型锁相环（PLL）的响应时间的装置，特别是包括IC内的反相类型的积分器的相位检测器和放大器的装置包括与放大器级联耦合的可控滤波器级 。 可控滤波器级包括滤波器部分和用于响应于模式确定控制信号选择性地旁路滤波器部分的开关装置。 在所描述的实施例中，PLL控制调谐器的本地振荡器的频率，并且第二滤波器部分具有幅度对频率响应，用于在微调模式期间增加PLL的响应时间，使得解调器可以继续正常地操作 在微调模式下。

公开(公告)号：US5739874A

公开(公告)日：1998-04-14

申请号：US579782

申请日：1995-12-28

申请人： David Mark Badger ,  John Sidney Stewart ,  Michael Anthony Pugel

发明人： David Mark Badger ,  John Sidney Stewart ,  Michael Anthony Pugel

IPC分类号： H04N5/44 ,  H03J1/00 ,  H03J7/02 ,  H03L7/107 ,  H04B1/26 ,  H04N5/455 ,  H04N5/46 ,  H04N5/50 ,  H04N7/20

CPC分类号： H03L7/0805 ,  H03J1/005 ,  H03L7/107

摘要： An economical tuning system for a digital satellite television receiver includes a phase locked loop (PLL) tuning control IC of the which is normally used in a tuning system of a conventional terrestrial broadcast or cable television reciever to control the frequency of the local oscillator (LO). Unfortunately, the PLL IC is only capable of changing the frequency of the LO in relatively large steps. As a result, the operation of a carrier recovery loop which demodulates the digitally encoded IF signal produced by the tuner may be interrupted during a fine tuning mode because the carrier recovery loop may not be able to track frequency changes of the LO. To reduce such possibility, the integrator filter associated with the PLL IC is modified to decrease the rate of change of the LO frequency during the fine tuning mode.

摘要翻译： 用于数字卫星电视接收机的经济调谐系统包括锁相环（PLL）调谐控制IC，其通常用于常规地面广播或有线电视接收机的调谐系统中，以控制本地振荡器（LO ）。 不幸的是，PLL IC只能在相对较大的步骤中改变LO的频率。 因此，由于载波恢复环路可能无法跟踪LO的频率变化，所以在微调模式期间，解调由调谐器产生的数字编码的IF信号的载波恢复环路的操作可能被中断。 为了减少这种可能性，修改了与PLL IC相关联的积分滤波器，以在微调模式期间降低LO频率的变化率。

公开(公告)号：US5686866A

公开(公告)日：1997-11-11

申请号：US504849

申请日：1995-07-20

申请人： David Mark Badger

发明人： David Mark Badger

IPC分类号： H04N5/44 ,  H03L7/093 ,  H03L7/10 ,  H03L7/107 ,  H03L7/085

CPC分类号： H03L7/10 ,  H03L7/107

摘要： A more rapid charging of an integrating capacitor of a PLL is provided when large frequency changes are desired. In one embodiment, the phase locked loop (PLL) circuit sinks or sources current to charge or discharge the integrating capacitor. A threshold voltage proportional to a current through the capacitor turns on an augmenting circuit which sinks or sources more current of the proper polarity to the integrating capacitor from an external source until a PLL lock is achieved. Once the lock is achieved, if a small correction current is required by the PLL, the small correction current is below a threshold required to actuate the augmenting circuit, and the PLL loop behaves in the usual manner as if the augmenting circuit were not present. In another embodiment, the integrating capacitor is reduced in value by switchably connecting a second capacitor in series with the integrating capacitor so that the total reduced capacitance of reduced value can be charged more quickly.

摘要翻译： 当需要大的频率变化时，提供PLL的积分电容器的更快速的充电。 在一个实施例中，锁相环（PLL）电路吸收或输出电流以对积分电容器进行充电或放电。 与通过电容器的电流成比例的阈值电压使得增加电路从外部源吸收或者从积分电容器吸收更多的适当极性的电流，直到达到PLL锁定。 一旦实现锁定，如果PLL需要小的校正电流，则小的校正电流低于启动增加电路所需的阈值，并且PLL环路以通常的方式表现为如同不存在增强电路。 在另一个实施例中，积分电容器的值通过可逆地连接与积分电容器串联的第二电容器来降低，从而能够更快地充电降低的总电容。

公开(公告)号：US5678211A

公开(公告)日：1997-10-14

申请号：US558761

申请日：1995-11-16

申请人： David Mark Badger

发明人： David Mark Badger

IPC分类号： H03J1/00 ,  H03J3/08 ,  H03J3/32 ,  H04B1/16

CPC分类号： H03J5/0263 ,  H03J1/005 ,  H03J3/08 ,  H03J3/32

摘要： The invention concerns an arrangement including a microprocessor controller, PROM memory, and a digital to analog converter (DAC) arrangement for generating a plurality of control voltages for trimming respective ones of a plurality of varactor controlled tunable filters. The controller couples digital control signals to the respective DACs which generate respective analog control voltages which are applied to the respective tunable filters. A tuning voltage generated by a closed control loop, such as phased locked loop also under the control of the controller, is combined with the output control voltages generated by the respective DAC's in a resistance divider arrangement.

摘要翻译： 本发明涉及一种包括微处理器控制器，PROM存储器和数模转换器（DAC）装置的装置，用于产生多个控制电压，用于修整多个变容二极管控制的可调谐滤波器中的相应的一个。 控制器将数字控制信号耦合到相应的DAC，DAC产生施加到各个可调谐滤波器的各自的模拟控制电压。 在控制器的控制下，闭合控制回路产生的调谐电压（例如定相锁定环路）与由各自的DAC在电阻分配装置中产生的输出控制电压组合。