公开(公告)号：US08406073B1

公开(公告)日：2013-03-26

申请号：US12928948

申请日：2010-12-22

申请人： Dinesh Somasekhar ,  Gunjan Pandya ,  Kevin Zhang ,  Fatih Hamzaoglu ,  Balaji Srinivasan ,  Swaroop Ghosh ,  Meterelliyoz Mesut

发明人： Dinesh Somasekhar ,  Gunjan Pandya ,  Kevin Zhang ,  Fatih Hamzaoglu ,  Balaji Srinivasan ,  Swaroop Ghosh ,  Meterelliyoz Mesut

IPC分类号： G11C8/00

CPC分类号： G11C11/4097 ,  G11C7/065 ,  G11C7/08 ,  G11C11/4091 ,  G11C11/4094

摘要： A hierarchical DRAM sensing apparatus and method which employs local bit line pairs and global bit lines. A word line selects the cells in a cluster of sense amplifiers, each of the amplifiers being associated with a pair of bit lines. One of the local bit lines is selected for coupling to global bit lines and a global sense amplifier. Clusters are located in a plurality of subarrays forming a bank with the global bit lines extending from each of the banks to the global sense amplifier.

摘要翻译： 采用本地位线对和全局位线的分级DRAM感测装置和方法。 字线选择感测放大器群集中的单元，每个放大器与一对位线相关联。 选择本地位线之一用于耦合到全局位线和全局读出放大器。 集群位于形成一个存储体的多个子阵列中，其中全局位线从每个存储体延伸到全局读出放大器。