公开(公告)号：US20140169106A1

公开(公告)日：2014-06-19

申请号：US13997591

申请日：2012-03-15

Applicant: Pramod Kolar ,  John Riley ,  Gunjan Pandya

Inventor： Pramod Kolar ,  John Riley ,  Gunjan Pandya

IPC: G11C7/12

CPC classification number: G11C7/12 ,  G11C7/10 ,  G11C7/1096 ,  G11C7/22

Abstract: A negative bitline write assist circuit includes a bias capacitor configured to facilitate driving the capacitance of a bitline. The negative bitline write assist circuit may be modularly replicated within a circuit to change the amount of negative voltage on the bitline during write operations. The bitline write assist circuit may be coupled directly to the bitline, removing the need to add a pull-down transistor to the write driver.

Abstract translation: 负位线写入辅助电路包括被配置为有助于驱动位线的电容的偏置电容器。 负位线写辅助电路可以在电路内模块化复制，以在写操作期间改变位线上的负电压量。 位线写辅助电路可以直接耦合到位线，从而不需要向写驱动器添加下拉晶体管。

公开(公告)号：US20050213370A1

公开(公告)日：2005-09-29

申请号：US10810093

申请日：2004-03-26

Applicant: Muhammad Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Ali Farhang ,  Gunjan Pandya ,  Vivek De

Inventor： Muhammad Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Ali Farhang ,  Gunjan Pandya ,  Vivek De

IPC: G11C11/41 ,  G11C11/419

CPC classification number: G11C11/419

Abstract: A SRAM memory cell comprising cross-coupled inverters, each cross-coupled inverter comprising a pull-up transistor, where the pull-up transistors are forward body biased during read operations. Forward body biasing improves the read stability of the memory cell. Other embodiments are described and claimed.

Abstract translation: 一种SRAM存储单元，包括交叉耦合的反相器，每个交叉耦合的反相器包括一个上拉晶体管，其中上拉晶体管在读取操作期间被正向偏置。 正向主体偏置改善了存储单元的读取稳定性。 描述和要求保护其他实施例。

公开(公告)号：US20060114711A1

公开(公告)日：2006-06-01

申请号：US11001870

申请日：2004-12-01

Applicant: Muhammad Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Gunjan Pandya ,  Vivek De

Inventor： Muhammad Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Gunjan Pandya ,  Vivek De

IPC: G11C11/00

CPC classification number: G11C11/419

Abstract: In one embodiment, a memory array is provided comprising one or more columns each comprising a plurality of bit cells divided into groups of bit cells with each group of bit cells controllably coupled to a separate bit line.

Abstract translation: 在一个实施例中，提供了包括一个或多个列的存储器阵列，每个列包括被分成位单元组的多个位单元，每组比特单元可控制地耦合到单独的位线。

公开(公告)号：US08406073B1

公开(公告)日：2013-03-26

申请号：US12928948

申请日：2010-12-22

Applicant: Dinesh Somasekhar ,  Gunjan Pandya ,  Kevin Zhang ,  Fatih Hamzaoglu ,  Balaji Srinivasan ,  Swaroop Ghosh ,  Meterelliyoz Mesut

Inventor： Dinesh Somasekhar ,  Gunjan Pandya ,  Kevin Zhang ,  Fatih Hamzaoglu ,  Balaji Srinivasan ,  Swaroop Ghosh ,  Meterelliyoz Mesut

IPC: G11C8/00

CPC classification number: G11C11/4097 ,  G11C7/065 ,  G11C7/08 ,  G11C11/4091 ,  G11C11/4094

Abstract: A hierarchical DRAM sensing apparatus and method which employs local bit line pairs and global bit lines. A word line selects the cells in a cluster of sense amplifiers, each of the amplifiers being associated with a pair of bit lines. One of the local bit lines is selected for coupling to global bit lines and a global sense amplifier. Clusters are located in a plurality of subarrays forming a bank with the global bit lines extending from each of the banks to the global sense amplifier.

Abstract translation: 采用本地位线对和全局位线的分级DRAM感测装置和方法。 字线选择感测放大器群集中的单元，每个放大器与一对位线相关联。 选择本地位线之一用于耦合到全局位线和全局读出放大器。 集群位于形成一个存储体的多个子阵列中，其中全局位线从每个存储体延伸到全局读出放大器。

公开(公告)号：US09378788B2

公开(公告)日：2016-06-28

申请号：US13997591

申请日：2012-03-15

Applicant: Pramod Kolar ,  John Riley ,  Gunjan Pandya

Inventor： Pramod Kolar ,  John Riley ,  Gunjan Pandya

IPC: G11C7/12 ,  G11C7/10

CPC classification number: G11C7/12 ,  G11C7/10 ,  G11C7/1096 ,  G11C7/22

Abstract: A negative bitline write assist circuit includes a bias capacitor configured to facilitate driving the capacitance of a bitline. The negative bitline write assist circuit may be modularly replicated within a circuit to change the amount of negative voltage on the bitline during write operations. The bitline write assist circuit may be coupled directly to the bitline, removing the need to add a pull-down transistor to the write driver.

Abstract translation: 负位线写入辅助电路包括被配置为有助于驱动位线的电容的偏置电容器。 负位线写辅助电路可以在电路内模块化复制，以在写操作期间改变位线上的负电压量。 位线写辅助电路可以直接耦合到位线，从而不需要向写驱动器添加下拉晶体管。