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公开(公告)号：US20190138341A1
公开(公告)日：2019-05-09
申请号：US16185833
申请日：2018-11-09
Inventor： Kwang Won KOH , Kang Ho KIM
IPC: G06F9/455 , G06F12/109 , G06F12/02
CPC classification number: G06F9/45558 , G06F12/0246 , G06F12/109 , G06F2009/45583 , G06F2009/45591 , G06F2212/1016 , G06F2212/151 , G06F2212/152 , G06F2212/7201
Abstract: The preset specification provides a method of managing a disaggregated memory in a virtual system. Herein, the disaggregated memory managing method includes: detecting a memory access pattern in a virtual machine node based on an operation of a virtual machine; and performing a memory operation by using a memory block in consideration of the memory access pattern, wherein the memory access pattern is variably set based on a time at which the operation of the virtual machine is performed, and the memory block dynamically changes in size based on the memory access pattern.
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公开(公告)号：US20190114079A1
公开(公告)日：2019-04-18
申请号：US16162107
申请日：2018-10-16
Inventor： Kang Ho KIM , Kwang Won KOH
Abstract: Disclosed is a method of managing a disaggregated memory. According to the present disclosure, the method includes: assigning at least one memory page to a local memory and a remote memory; checking a request for access to the memory page; checking whether a target performance ratio required in service is satisfied or not when the memory page requested to be accessed is assigned to the remote memory; predicting a size of the local memory on the basis of an LRU distance-based histogram when the target performance ratio is not satisfied; and reassigning the memory page requested to be accessed in consideration of the predicted size of the local memory.
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公开(公告)号：US20170329642A1
公开(公告)日：2017-11-16
申请号：US15234785
申请日：2016-08-11
Inventor： Jin Mee KIM , Kwang Won KOH , Kang Ho KIM , Jeong Hwan LEE , Seung Hyub JEON , Sung In JUNG , Yeon Jeong JEONG , Seung Jun CHA
Abstract: Provided is a many-core system including a resource unit including a resource needed for execution of an operating system and a resource needed for execution of a lightweight kernel, a programing constructing unit configured to convert an input program into an application program and to load the application program into the resource unit, a run-time management unit configured to manage a running environment for executing the application program, and a self-organization management unit configured to monitor the application program and the resources in the resource unit, to dynamically adjust the running environment to prevent a risk factor from occurring during the execution of the application program, and to cure a risk factor which occurred.
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公开(公告)号：US20240295987A1
公开(公告)日：2024-09-05
申请号：US18660095
申请日：2024-05-09
Inventor： Kwang-Won KOH , Kang Ho KIM , Changdae KIM , Taehoon KIM
IPC: G06F3/06
CPC classification number: G06F3/0656 , G06F3/0604 , G06F3/0679
Abstract: A memory access method and device are provided. A memory access method may include: identifying, when an access to a page of a remote memory occurs, a type of the access; allocating a sparse buffer when the access is a sparse write; storing data for the sparse write in the sparse buffer; storing an address for the sparse write as a key and the sparse buffer as a value in a buffer table; and updating an instruction pointer to point to a next instruction.
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Patent Agency Ranking
公开(公告)号：US20170269966A1
公开(公告)日：2017-09-21
申请号：US15462683
申请日：2017-03-17
Inventor： Kang Ho KIM , Kwang Won KOH , Jin Mee KIM , Jeong Hwan LEE , Seung Hyub JEON , Sung In JUNG , Yeon Jeong JEONG , Seung Jun CHA
CPC classification number: G06F9/4881 , G06F1/329 , G06F9/5027 , G06F9/54 , G06F2209/502
Abstract: Provided is a method of scheduling threads in a many-cores system. The method includes generating a thread map where a connection relationship between a plurality of threads is represented by a frequency of inter-process communication (IPC) between threads, generating a core map where a connection relationship between a plurality of cores is represented by a hop between cores, and respectively allocating the plurality of threads to the plurality of cores defined by the core map, based on a thread allocation policy defining a mapping rule between the thread map and the core map.
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公开(公告)号：US20220197764A1
公开(公告)日：2022-06-23
申请号：US17542324
申请日：2021-12-03
Inventor： SUNGIK JUN , Kwang-Won KOH , Kang Ho KIM , Changdae KIM , Taehoon KIM
Abstract: Disclosed is a quantum diagnostic circuit, which includes an input unit having an input of at least first to fourth qubits, a diagnostic circuit unit receiving the first to fourth qubits from the input unit and providing a quantum superposition and a quantum entanglement, and an output unit receiving an output of the diagnostic circuit unit and determining whether the output is in a Bell-state, and the diagnostic circuit unit includes a Hadamard gate processing the first qubit to provide the quantum superposition of the first to fourth qubits, a first CNOT gate providing the quantum entanglement between an output of the Hadamard gate and the second qubit, a second CNOT gate providing the quantum entanglement between an output of the first CNOT gate and the third qubit, and a third CNOT gate providing the quantum entanglement between an output of the second CNOT gate and the fourth qubit.
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公开(公告)号：US20210287760A1
公开(公告)日：2021-09-16
申请号：US17070452
申请日：2020-10-14
Inventor： Changdae KIM , Kwang-Won KOH , Kang Ho KIM
IPC: G16B30/10
Abstract: An apparatus for genome sequence alignment attempts a search for the hash tables to align a target nucleotide sequence, from a hash table having a large seed size to a hash table having a small seed size, and when there is at least one matched seed to the target nucleotide sequence on a hash table, aligns the target nucleotide sequence by using candidate positions from the hash table without further hash table searching.
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公开(公告)号：US20220365712A1
公开(公告)日：2022-11-17
申请号：US17741187
申请日：2022-05-10
Inventor： Kwang-Won KOH , Kang Ho KIM , Changdae KIM , Taehoon KIM
IPC: G06F3/06
Abstract: A memory access method and device are provided. A memory access method may include: identifying, when an access to a page of a remote memory occurs, a type of the access; allocating a sparse buffer when the access is a sparse write; storing data for the sparse write in the sparse buffer; storing an address for the sparse write as a key and the sparse buffer as a value in a buffer table; and updating an instruction pointer to point to a next instruction.
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公开(公告)号：US20220300331A1
公开(公告)日：2022-09-22
申请号：US17517284
申请日：2021-11-02
Inventor： Changdae KIM , Kwang-Won KOH , Kang Ho KIM , Taehoon KIM
Abstract: An apparatus for memory integrated management in a cluster system including a plurality of physical nodes connected to each other by a network determines one of the plurality of physical nodes as a node to place a new virtual machine, allocates the first type of memory allocated to the one physical node to the new virtual machine as much as the memory capacity required by the new virtual machine, and distributes the second type of memory to a plurality of virtual machines running on the plurality of physical nodes by integrating and managing the second type of memory allocated to each of the plurality of physical nodes. In this case, the access speed of the second type of memory is faster than that of the first type of memory.
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