公开(公告)号：US20210408265A1

公开(公告)日：2021-12-30

申请号：US17355977

申请日：2021-06-23

Applicant: Electronics and Telecommunications Research Institute

Inventor： Kun Sik PARK ,  Jong Il WON ,  Doo Hyung CHO ,  Hyun Gyu JANG ,  Dong Yun JUNG

IPC: H01L29/66 ,  H01L29/745 ,  H01L29/749

Abstract: The present invention forms an off-FET channel having a uniform and short length by using a self-align process of a method of forming and recessing a spacer, thereby enhancing the current driving capability of an off-FET and the uniformity of a device operation.

公开(公告)号：US20220020671A1

公开(公告)日：2022-01-20

申请号：US17380583

申请日：2021-07-20

Applicant: Electronics and Telecommunications Research Institute

Inventor： Dong Yun JUNG ,  Hyun Gyu JANG ,  Sung Kyu KWON ,  Kun Sik PARK ,  Jong Il WON ,  Seong Hyun LEE ,  Jong Won LIM ,  Doo Hyung CHO

IPC: H01L23/495 ,  H01L23/00

Abstract: The present invention minimizes parasitic inductance at the time of packaging a semiconductor that requires high efficiency and high-speed switching driving. In implementing a semiconductor package composed of one or more switching devices and one or more diode devices, the present invention provides a flip-stack structure in which a switching device is mounted on an insulating substrate or a metal frame, a flat metal is bonded onto the switching device, and a diode device is flipped and stacked on the flat metal, and accordingly, the flat metal with a large area is used for connection between the devices and between the devices and the insulating substrate, thereby minimizing parasitic inductance generated at a time of semiconductor packaging and automating the entire process of the semiconductor packaging.