Abstract:
A ceramic stacked semiconductor package and a method of packaging a ceramic stacked semiconductor is disclosed. Inner walls of junctions are formed between ceramic layers and a molding resin to have a non-uniform boundary shape (e.g., Z shape, an uneven shape, a zigzag shape, etc.) so that bonding areas and lengths of the molding resin and the ceramic layers are increased, and thus adhesion is improved and movement paths of moisture are increased, thereby improving anti-humidity property and reliability of the semiconductor package. Further, by arranging via-holes at different positions for each layer so as not to overlap each other between the layers, movement paths of moisture passing through the via-holes are increased, and thus the anti-humidity property and reliability of the stacked package are additionally improved.
Abstract:
The present invention minimizes parasitic inductance at the time of packaging a semiconductor that requires high efficiency and high-speed switching driving. In implementing a semiconductor package composed of one or more switching devices and one or more diode devices, the present invention provides a flip-stack structure in which a switching device is mounted on an insulating substrate or a metal frame, a flat metal is bonded onto the switching device, and a diode device is flipped and stacked on the flat metal, and accordingly, the flat metal with a large area is used for connection between the devices and between the devices and the insulating substrate, thereby minimizing parasitic inductance generated at a time of semiconductor packaging and automating the entire process of the semiconductor packaging.
Abstract:
A nonvolatile memory and a method of manufacturing a nonvolatile memory are disclosed. A nonvolatile memory according to an exemplary embodiment may include a deep well formed on a substrate, a first well formed within the deep well, a second well formed separately from the first well within the deep well, a first metal-oxide-semiconductor field-effect transistor (MOSFET) formed on the first well, and a second MOSFET formed on the second well. According to a method of manufacturing a nonvolatile memory according to an exemplary embodiment, a well region of a control MOSFET of a memory cell may be shared with a control MOSFET of an adjacent memory cell, or a well region of a tunneling MOSFET of a memory cell may be shared with a tunneling MOSFET of an adjacent memory cell, thereby reducing an area of the memory cells. Further, the nonvolatile memory according to the exemplary embodiment may constantly maintain a voltage of a shared well region in the tunneling MOSFET and apply a different voltage to a source/drain from that of an adjacent cell, thereby recording data only in the selected memory cell or deleting recorded data from the selected memory cell while sharing the well region.
Abstract:
A MOS controlled thyristor device according to the concept of the present invention includes a substrate comprising a first surface and a second surface, which face each other, gate patterns disposed on the first surface, a cathode electrode configured to cover the gate patterns, and an anode electrode disposed on the second surface, The substrate includes a lower emitter layer having a first conductive type, a lower base layer having a second conductive type on the lower emitter layer, an upper base region provided in an upper portion of the lower emitter layer and having a first conductive type, wherein the upper base region is configured to expose a portion of a top surface of the lower base layer, an upper emitter region having a second conductive type and provided in an upper portion of the upper base region, a first doped region having a first conductive type and a second doped region surrounded by the first doped region and having a second conductive type, wherein the first and second doped regions are provided in an upper portion of the upper emitter region, and a first doping pattern having a first conductive type, which is provided on one surface of the upper portion of the upper emitter region. The first doping pattern is interposed between the upper base region and the first doped region along a first direction parallel to the top surface of the substrate. The first doping pattern is configured to expose a top surface of the upper emitter region on the other surface of the upper portion of the upper emitter region. Each of the gate patterns is configured to cover portions of an exposed top surface of the lower base layer, an exposed top surface of the upper base layer, an exposed top surface of the upper emitter region, a top surface of the first doping pattern, and a top surface of the first doped region. The cathode electrode is configured to cover portions of top and side surfaces of the gate pattern, a top surface of the second doped region, and a top surface of the first doped region. The first conductive type and the second conductive type are different from each other.
Abstract:
The present invention forms an off-FET channel having a uniform and short length by using a self-align process of a method of forming and recessing a spacer, thereby enhancing the current driving capability of an off-FET and the uniformity of a device operation.
Abstract:
There is provided a battery system including: a controller; a main switch controlled by the controller to supply or cut off a voltage of a battery to a load; and a semiconductor pre-charger module including a semiconductor switch connected in parallel with the main switch and configured to supply or cut off the voltage of the battery to the load according to a control signal output from the controller, and a semiconductor switch driver configured to receive the control signal from the controller and output a single pulse signal for driving the semiconductor switch to turn on and off the semiconductor switch. Here, the semiconductor switch driver of the semiconductor pre-charger module includes an isolation element configured to electrically isolate the controller and the battery voltage, and the semiconductor switch of the semiconductor pre-charger module is a MOS-controlled thyristor (MCT).
Abstract:
The apparatus for ESD test includes a micro-controller unit client, a low voltage supply configured to output a low voltage on the basis of control by the micro-controller unit, a high voltage supply configured to output a high voltage on the basis of control by the micro-controller unit, and an ESD generator configured to generate an ESD voltage for an ESD test of a device under test (DUT) by using the low voltage and the high voltage, on the basis of control by the micro-controller unit. The ESD generator is a semiconductor integrated circuit module where a charging semiconductor switch, a discharging semiconductor switch, a switch driving block controlling a switching operation of each of the charging semiconductor switch and the discharging semiconductor switch, and a plurality of passive elements connected to the charging semiconductor switch and the discharging semiconductor switch are implemented as package, for generating the ESD voltage.
Abstract:
Provided is a Schottky diode including a substrate, a drift layer on the substrate, the drift layer comprising an active region and a periphery positioned at an edge of the active region, a junction termination layer on a boundary between the active region and the periphery, a first metal layer configured to cover a part of the active region and a part of the junction termination layer, and a second metal layer configured to cover the first metal layer and the active region, wherein the first metal layer and the second metal layer contact the drift layer to provide a Schottky junction, and the first metal layer has a higher Schottky barrier height than the second metal layer.