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    NON-VOLATILE MEMORY (NVM) AND METHOD FOR MANUFACTURING THEREOF
    3.
    发明申请
    NON-VOLATILE MEMORY (NVM) AND METHOD FOR MANUFACTURING THEREOF 有权
    非易失性存储器（NVM）及其制造方法

    公开(公告)号：US20130294172A1

    公开(公告)日：2013-11-07

    申请号：US13871300

    申请日：2013-04-26

    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

    Inventor： Kun Sik PARK ,  Kyu Ha BAEK

    IPC: G11C16/04 ,  H01L29/788

    CPC classification number: G11C16/0425 ,  G11C16/0441 ,  G11C2216/10 ,  H01L27/11558 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7881

    Abstract: A nonvolatile memory and a method of manufacturing a nonvolatile memory are disclosed. A nonvolatile memory according to an exemplary embodiment may include a deep well formed on a substrate, a first well formed within the deep well, a second well formed separately from the first well within the deep well, a first metal-oxide-semiconductor field-effect transistor (MOSFET) formed on the first well, and a second MOSFET formed on the second well. According to a method of manufacturing a nonvolatile memory according to an exemplary embodiment, a well region of a control MOSFET of a memory cell may be shared with a control MOSFET of an adjacent memory cell, or a well region of a tunneling MOSFET of a memory cell may be shared with a tunneling MOSFET of an adjacent memory cell, thereby reducing an area of the memory cells. Further, the nonvolatile memory according to the exemplary embodiment may constantly maintain a voltage of a shared well region in the tunneling MOSFET and apply a different voltage to a source/drain from that of an adjacent cell, thereby recording data only in the selected memory cell or deleting recorded data from the selected memory cell while sharing the well region.

    Abstract translation: 公开了非易失性存储器和制造非易失性存储器的方法。 根据示例性实施例的非易失性存储器可以包括在衬底上形成的深阱，在深阱内形成的第一阱，与深阱内的第一阱分开形成的第二阱，第一金属氧化物半导体场 - 形成在第一阱上的效应晶体管（MOSFET）和形成在第二阱上的第二MOSFET。 根据根据示例性实施例的制造非易失性存储器的方法，存储器单元的控制MOSFET的阱区可以与相邻存储器单元的控制MOSFET或存储器的隧道MOSFET的阱区共享 单元可以与相邻存储器单元的隧道MOSFET共享，从而减小存储单元的面积。 此外，根据示例性实施例的非易失性存储器可以恒定地保持隧道MOSFET中的共享阱区的电压，并且向相邻单元的源极/漏极施加不同的电压，从而仅将数据记录在所选存储单元 或者在共享井区域的同时从所选存储单元中删除记录数据。

    MOS(METAL OXIDE SILICON) CONTROLLED THYRISTOR DEVICE
    4.
    发明申请
    MOS(METAL OXIDE SILICON) CONTROLLED THYRISTOR DEVICE 有权

    公开(公告)号：US20230087416A1

    公开(公告)日：2023-03-23

    申请号：US17792070

    申请日：2021-06-10

    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

    Inventor： Kun Sik PARK ,  Jong II WON ,  Doo Hyung CHO ,  Dong Yun JUNG ,  Hyun GYu Jang

    IPC: H01L29/745 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

    Abstract: A MOS controlled thyristor device according to the concept of the present invention includes a substrate comprising a first surface and a second surface, which face each other, gate patterns disposed on the first surface, a cathode electrode configured to cover the gate patterns, and an anode electrode disposed on the second surface, The substrate includes a lower emitter layer having a first conductive type, a lower base layer having a second conductive type on the lower emitter layer, an upper base region provided in an upper portion of the lower emitter layer and having a first conductive type, wherein the upper base region is configured to expose a portion of a top surface of the lower base layer, an upper emitter region having a second conductive type and provided in an upper portion of the upper base region, a first doped region having a first conductive type and a second doped region surrounded by the first doped region and having a second conductive type, wherein the first and second doped regions are provided in an upper portion of the upper emitter region, and a first doping pattern having a first conductive type, which is provided on one surface of the upper portion of the upper emitter region. The first doping pattern is interposed between the upper base region and the first doped region along a first direction parallel to the top surface of the substrate. The first doping pattern is configured to expose a top surface of the upper emitter region on the other surface of the upper portion of the upper emitter region. Each of the gate patterns is configured to cover portions of an exposed top surface of the lower base layer, an exposed top surface of the upper base layer, an exposed top surface of the upper emitter region, a top surface of the first doping pattern, and a top surface of the first doped region. The cathode electrode is configured to cover portions of top and side surfaces of the gate pattern, a top surface of the second doped region, and a top surface of the first doped region. The first conductive type and the second conductive type are different from each other.

    SEMICONDUCTOR PRE-CHARGER MODULE IN BATTERY SYSTEM
    6.
    发明公开
    SEMICONDUCTOR PRE-CHARGER MODULE IN BATTERY SYSTEM 审中-公开

    公开(公告)号：US20230231404A1

    公开(公告)日：2023-07-20

    申请号：US18153155

    申请日：2023-01-11

    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

    Inventor： Dong Yun JUNG ,  Kun Sik PARK ,  JONG IL WON ,  Hyun-Gyu JANG ,  Doohyung CHO ,  Jong-Won LIM

    IPC: H02J7/00

    CPC classification number: H02J7/007182 ,  H02J7/0047 ,  H02J7/00711 ,  H02J7/00714 ,  H02J2207/20

    Abstract: There is provided a battery system including: a controller; a main switch controlled by the controller to supply or cut off a voltage of a battery to a load; and a semiconductor pre-charger module including a semiconductor switch connected in parallel with the main switch and configured to supply or cut off the voltage of the battery to the load according to a control signal output from the controller, and a semiconductor switch driver configured to receive the control signal from the controller and output a single pulse signal for driving the semiconductor switch to turn on and off the semiconductor switch. Here, the semiconductor switch driver of the semiconductor pre-charger module includes an isolation element configured to electrically isolate the controller and the battery voltage, and the semiconductor switch of the semiconductor pre-charger module is a MOS-controlled thyristor (MCT).

    APPARATUS FOR ELECTROSTATIC DISCHARGE TEST
    7.
    发明申请
    APPARATUS FOR ELECTROSTATIC DISCHARGE TEST 有权

    公开(公告)号：US20220299554A1

    公开(公告)日：2022-09-22

    申请号：US17510856

    申请日：2021-10-26

    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

    Inventor： Dong Yun JUNG ,  Hyun Gyu JANG ,  Kun Sik PARK ,  JONG IL WON ,  Sung Kyu KWON ,  Jong Won LIM ,  Doo Hyung CHO

    IPC: G01R31/00

    Abstract: The apparatus for ESD test includes a micro-controller unit client, a low voltage supply configured to output a low voltage on the basis of control by the micro-controller unit, a high voltage supply configured to output a high voltage on the basis of control by the micro-controller unit, and an ESD generator configured to generate an ESD voltage for an ESD test of a device under test (DUT) by using the low voltage and the high voltage, on the basis of control by the micro-controller unit. The ESD generator is a semiconductor integrated circuit module where a charging semiconductor switch, a discharging semiconductor switch, a switch driving block controlling a switching operation of each of the charging semiconductor switch and the discharging semiconductor switch, and a plurality of passive elements connected to the charging semiconductor switch and the discharging semiconductor switch are implemented as package, for generating the ESD voltage.

    SCHOTTKY DIODE
    8.
    发明申请
    SCHOTTKY DIODE 审中-公开
    肖特基二极管

    公开(公告)号：US20160284872A1

    公开(公告)日：2016-09-29

    申请号：US15080338

    申请日：2016-03-24

    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

    Inventor： Kun Sik PARK ,  Jong II WON ,  Doo Hyung CHO

    IPC: H01L29/872 ,  H01L29/16 ,  H01L29/06

    CPC classification number: H01L29/872 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/402 ,  H01L29/417 ,  H01L29/6606

    Abstract: Provided is a Schottky diode including a substrate, a drift layer on the substrate, the drift layer comprising an active region and a periphery positioned at an edge of the active region, a junction termination layer on a boundary between the active region and the periphery, a first metal layer configured to cover a part of the active region and a part of the junction termination layer, and a second metal layer configured to cover the first metal layer and the active region, wherein the first metal layer and the second metal layer contact the drift layer to provide a Schottky junction, and the first metal layer has a higher Schottky barrier height than the second metal layer.

    Abstract translation: 提供了一种肖特基二极管，其包括衬底，衬底上的漂移层，漂移层包括有源区和位于有源区的边缘处的周边，活性区和周边之间的边界上的结终端层， 第一金属层，其被配置为覆盖所述有源区的一部分和所述结终端层的一部分;以及第二金属层，被配置为覆盖所述第一金属层和所述有源区，其中所述第一金属层和所述第二金属层接触 所述漂移层提供肖特基结，并且所述第一金属层具有比所述第二金属层更高的肖特基势垒高度。

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