公开(公告)号：US20220139479A1

公开(公告)日：2022-05-05

申请号：US17088608

申请日：2020-11-04

Applicant: Elite Semiconductor Microelectronics Technology Inc.

Inventor： Yu-Tao Lin ,  Tse-Hua Yao ,  Yi-Fan Chen

IPC: G11C29/38 ,  G06F3/06 ,  G11C8/06

Abstract: A memory test circuit comprising: a first latch circuit for receiving a first input address and an error indication signal to generate a first address; a first E-fuse group for receiving the first address to generate an output address; a second latch circuit for receiving the error indication signal; a second E-fuse group for generating an error indication signal according to an output of the second latch circuit which is generated according to the fault indication signal; and a comparison circuit for activating the second latch circuit according to a relation between the first address and a second input address and a state of the first latch circuit or the first E-fuse group.

公开(公告)号：US11127477B1

公开(公告)日：2021-09-21

申请号：US17076827

申请日：2020-10-22

Applicant: Elite Semiconductor Microelectronics Technology Inc.

Inventor： Tse-Hua Yao ,  Yi-Fan Chen

IPC: G11C17/16 ,  G11C29/00 ,  G11C29/02

Abstract: An E-fuse circuit comprising: an E-fuse group, comprising a plurality of E-fuse sections, wherein each one of the E-fuse sections comprises a plurality of E-fuses; a multi-mode latch circuit, configured to receive an input signal to generate a first output signal in a burn in mode, and configured to receive an address to be compared to generate a second output signal in a normal mode; a first logic circuit group, configured to receive a first part of bits of the first output signal to generate a control signal in the burn in mode; and a second logic circuit group, configured to receive the control signal and a second part of bits of the first output signal to generate a selection signal in the burn in mode, to select which one of the E-fuse sections is activated.

公开(公告)号：US11335427B1

公开(公告)日：2022-05-17

申请号：US17088608

申请日：2020-11-04

Applicant: Elite Semiconductor Microelectronics Technology Inc.

Inventor： Yu-Tao Lin ,  Tse-Hua Yao ,  Yi-Fan Chen

IPC: G11C8/06 ,  G11C29/38 ,  G06F3/06

Abstract: A memory test circuit comprising: a first latch circuit for receiving a first input address and an error indication signal to generate a first address; a first E-fuse group for receiving the first address to generate an output address; a second latch circuit for receiving the error indication signal; a second E-fuse group for generating an error indication signal according to an output of the second latch circuit which is generated according to the fault indication signal; and a comparison circuit for activating the second latch circuit according to a relation between the first address and a second input address and a state of the first latch circuit or the first E-fuse group.

公开(公告)号：US11892521B2

公开(公告)日：2024-02-06

申请号：US17406121

申请日：2021-08-19

Applicant: ELITE SEMICONDUCTOR MICROELECTRONICS TECHNOLOGY INC.

Inventor： Tse-Hua Yao

IPC: G01R31/68 ,  G01R1/067 ,  H01L23/525

CPC classification number: G01R31/68 ,  G01R1/06794 ,  H01L23/5256

Abstract: A semiconductor device with contact check circuitry is provided. The semiconductor device includes a plurality of pads, an internal circuit, and a contact check circuit. The plurality of pads includes a first pad and a second pad. The internal circuit is coupled to the plurality of pads. The contact check circuit, at least coupled to the first pad and the second pad, is used for checking, when the semiconductor device is under test, contact connections to the first pad and the second pad to generate a check result signal according to comparison of a first test signal and a second test signal received from the first pad and the second pad with at least one reference signal.