公开(公告)号：US11245408B2

公开(公告)日：2022-02-08

申请号：US17151673

申请日：2021-01-19

Applicant: FARADAY TECHNOLOGY CORPORATION ,  Faraday Technology Corp.

Inventor： Feng Xu ,  Chih-Yuan Hung ,  Meng Zhao

IPC: H03M1/06 ,  H03M1/00

Abstract: A Successive Approximation Register Analog-to-Digital Converter (SAR ADC) is disclosed. The SAR ADC includes a switched capacitor array, a buffer, a comparator and a control logic circuit. The switched capacitor array is arranged to sample an input signal according to a switch control signal to generate a sampling signal. The buffer is arranged to generate a common mode voltage. The comparator is arranged to receive the sampling signal and the common mode voltage in order to generate a comparison result. The control logic circuit is arranged to generate an output signal according to the comparison result, and generate the switch control signal to control the switched capacitor array. The control logic circuit further generates an operation control signal to adjust a Miller compensation capacitor inside the buffer. An associated control method is also disclosed.

公开(公告)号：US10090853B1

公开(公告)日：2018-10-02

申请号：US15867734

申请日：2018-01-11

Applicant: Faraday Technology Corp.

Inventor： Shu-Dong Wu ,  Feng Xu

IPC: H03M1/38 ,  H03M1/14 ,  H03M1/46 ,  H03M1/40

Abstract: An analog-to-digital conversion device is provided for converting an input signal pair to generate an output signal. The analog-to-digital conversion device includes switch groups, capacitors, a comparator, and a controller. The switch groups receive the input signal pair and reference voltages, and selects to output one of the input signal pair and the reference voltages according to a control signal to generate selection voltages respectively. The capacitors receive the selection voltages respectively and generate a first comparison voltage and a second comparison voltage. The comparator compares the first comparison voltage and the second comparison voltage to generate a comparison result signal. The controller sets conversion times for converting bits of the output signal according to the comparison result signal, wherein at least two of the conversion times are different.

公开(公告)号：US10833674B2

公开(公告)日：2020-11-10

申请号：US16554652

申请日：2019-08-29

Applicant: Faraday Technology Corp.

Inventor： Feng Xu ,  Shu Dong Wu ,  Zhen Liang Zhang

IPC: H03K17/687 ,  H03K19/20 ,  H03M1/12

Abstract: A switch device including a switch circuit and switch controller. The switch circuit comprises first and second switches to selectively enable a path between an input terminal and an output terminal. The switch controller refers to a selection signal and a switch signal to respectively generate a first switch control signal at a first switch control signal output terminal and a second switch control signal at a second switch control signal output terminal. When the voltage level of an input signal at the input terminal is larger than a power voltage, the switch controller generates the first switch control signal and the second switch control signal capable of turning off the switch circuit. When the voltage level of the input signal is not larger than the power voltage, the switch controller generates the first switch control signal and the second switch control signal according to the switch signal.

公开(公告)号：US20210305990A1

公开(公告)日：2021-09-30

申请号：US17151673

申请日：2021-01-19

Applicant: FARADAY TECHNOLOGY CORPORATION ,  Faraday Technology Corp.

Inventor： Feng Xu ,  Chih-Yuan Hung ,  MENG ZHAO

IPC: H03M1/06

Abstract: A Successive Approximation Register Analog-to-Digital Converter (SAR ADC) is disclosed. The SAR ADC includes a switched capacitor array, a buffer, a comparator and a control logic circuit. The switched capacitor array is arranged to sample an input signal according to a switch control signal to generate a sampling signal. The buffer is arranged to generate a common mode voltage. The comparator is arranged to receive the sampling signal and the common mode voltage in order to generate a comparison result. The control logic circuit is arranged to generate an output signal according to the comparison result, and generate the switch control signal to control the switched capacitor array. The control logic circuit further generates an operation control signal to adjust a Miller compensation capacitor inside the buffer. An associated control method is also disclosed.

公开(公告)号：US20200304120A1

公开(公告)日：2020-09-24

申请号：US16554652

申请日：2019-08-29

Applicant: Faraday Technology Corp.

Inventor： Feng Xu ,  Shu Dong Wu ,  Zhen Liang Zhang

IPC: H03K17/687 ,  H03K19/20

Abstract: A switch device including a switch circuit and switch controller. The switch circuit comprises first and second switches to selectively enable a path between an input terminal and an output terminal. The switch controller refers to a selection signal and a switch signal to respectively generate a first switch control signal at a first switch control signal output terminal and a second switch control signal at a second switch control signal output terminal. When the voltage level of an input signal at the input terminal is larger than a power voltage, the switch controller generates the first switch control signal and the second switch control signal capable of turning off the switch circuit. When the voltage level of the input signal is not larger than the power voltage, the switch controller generates the first switch control signal and the second switch control signal according to the switch signal.