公开(公告)号：US20250020712A1

公开(公告)日：2025-01-16

申请号：US18349780

申请日：2023-07-10

Applicant: GAN SYSTEMS INC.

Inventor： Iman ABDALI MASHHADI ,  Thomas William MACELWEE ,  Mohammad BOZORGI ,  Ting-Hsiang HSU ,  Meng-ta YOU ,  Regina Inyangat AKUDO ,  Yueh Lin CHIANG

IPC: G01R31/26

Abstract: Wafer testing of a power transistor for a current property of the power transistor. Wafer testing of a power transistor is performed by using a sense transistor constructed using the same epitaxial stack as was used to construct the power transistor. The current property of the sense transistor is then measured, and the current property of the power transistor can be determined from that measurement. Furthermore, the sense transistor is pre-conditioned prior to the measurement by alternately turning on and off the sense transistor multiple cycles while allowing a source terminal of the power transistor to float. This simulates operating conditions of the power transistor, thereby allowing for measurement of the current property of the power transistor as it would likely be in operation.