公开(公告)号：US20240282827A1

公开(公告)日：2024-08-22

申请号：US18172916

申请日：2023-02-22

Applicant: GAN SYSTEMS INC.

Inventor： Marco A. ZUNIGA ,  Thomas William MACELWEE ,  Rohan SAMSI ,  Lucas Andrew Milner ,  Vineet Unni ,  Jayasimha S. PRASAD ,  Ashutosh Ravindra JOHARAPURKAR ,  Ramesh G. KARPUR

IPC: H01L29/40 ,  H01L29/20 ,  H01L29/201 ,  H01L29/778

CPC classification number: H01L29/402 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/7786

Abstract: The biasing of one or more field plates of a high electron mobility transistor (a HEMT) with a non-zero voltage to thereby affect the electric field profile of the HEMT. The non-zero voltage may be a constant DC voltage, or perhaps may be a voltage that changes over time. The use of a non-zero voltage allows for greater ability to regulate and reduce the electric field occurring in the semiconductor channel region, especially at the field plate. Further, when the electric field occurring at the field plate is reduced, the overall size of the HEMT can also be reduced as compared to applying a zero voltage to the field plate. Alternatively, or in addition, applying a non-zero voltage to the field plate allows the voltage levels handled by the HEMT to be increased as compared to simply grounding the field plate.

公开(公告)号：US20240393374A1

公开(公告)日：2024-11-28

申请号：US18322441

申请日：2023-05-23

Applicant: GAN SYSTEMS INC.

Inventor： Lucas Andrew MILNER ,  Marco A. ZUNIGA ,  Nan XING ,  Robert Wayne MOUNGER ,  Edward MACROBBIE ,  Sridhar RAMASWAMY ,  Ahmad MIZANNOJEHDEHI ,  Thomas William MACELWEE

IPC: G01R19/00

Abstract: A current sense circuit that allows for accurate sensing of a power current that flows through a power transistor as the power transistor ages. The circuit includes the power transistor, a sense transistor and a pull-up component. The control nodes of the power transistor and the sense transistor are connected, causing the power transistor and sense transistor to be on or off simultaneously. The pull-up component is connected between the input node of the power transistor and the input node of the sense transistor. When power is provided to the pull-up component, and when each of the power transistor and sense transistor are off, the pull-up component forces a voltage present at the sense transistor input node to be approximately equal to a voltage present at the power transistor input node, causing the sense and power transistors to age together.

公开(公告)号：US20250020712A1

公开(公告)日：2025-01-16

申请号：US18349780

申请日：2023-07-10

Applicant: GAN SYSTEMS INC.

Inventor： Iman ABDALI MASHHADI ,  Thomas William MACELWEE ,  Mohammad BOZORGI ,  Ting-Hsiang HSU ,  Meng-ta YOU ,  Regina Inyangat AKUDO ,  Yueh Lin CHIANG

IPC: G01R31/26

Abstract: Wafer testing of a power transistor for a current property of the power transistor. Wafer testing of a power transistor is performed by using a sense transistor constructed using the same epitaxial stack as was used to construct the power transistor. The current property of the sense transistor is then measured, and the current property of the power transistor can be determined from that measurement. Furthermore, the sense transistor is pre-conditioned prior to the measurement by alternately turning on and off the sense transistor multiple cycles while allowing a source terminal of the power transistor to float. This simulates operating conditions of the power transistor, thereby allowing for measurement of the current property of the power transistor as it would likely be in operation.

公开(公告)号：US20240413234A1

公开(公告)日：2024-12-12

申请号：US18331071

申请日：2023-06-07

Applicant: GAN SYSTEMS INC.

Inventor： Marco A. ZUNIGA ,  Thomas William MACELWEE ,  Vineet UNNI ,  Claudio Andres CANIZARES

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/417 ,  H03K17/687

Abstract: A transistor structure that includes multiple heterojunction layer sets, each generating a two-dimensional electron gas (2DEG), such that the transistor structure has a stack of 2DEGs that may be used to conduct between source and drain. A terminal is provided proximate an uppermost 2DEG to control whether the uppermost 2DEG is continuous between a source contact and a source plug. A source plug connects the uppermost 2DEG with the next 2DEG, and a drain plug also connects the uppermost 2DEG with the next 2DEG. Thus, the gate terminal may control the flow of current in sub-surface 2DEGs between the source and drain.