WAFER TESTING FOR CURRENT PROPERTY OF A POWER TRANSISTOR

    公开(公告)号:US20250020712A1

    公开(公告)日:2025-01-16

    申请号:US18349780

    申请日:2023-07-10

    Abstract: Wafer testing of a power transistor for a current property of the power transistor. Wafer testing of a power transistor is performed by using a sense transistor constructed using the same epitaxial stack as was used to construct the power transistor. The current property of the sense transistor is then measured, and the current property of the power transistor can be determined from that measurement. Furthermore, the sense transistor is pre-conditioned prior to the measurement by alternately turning on and off the sense transistor multiple cycles while allowing a source terminal of the power transistor to float. This simulates operating conditions of the power transistor, thereby allowing for measurement of the current property of the power transistor as it would likely be in operation.

    SELECTIVE GATE OVERDRIVE OF TRANSISTOR
    2.
    发明公开

    公开(公告)号:US20240297230A1

    公开(公告)日:2024-09-05

    申请号:US18177592

    申请日:2023-03-02

    CPC classification number: H01L29/41766 H01L29/1066 H01L29/2003 H01L29/66462

    Abstract: Overdriving a power field-effect transistor. In response to a detection that the power field-effect transistor has entered the saturation region, the gate node of the power field-effect transistor is overdriven with a higher voltage. The detection of whether the power field-effect transistor is within the saturation region is done with a sense field-effect transistor. This sense field-effect transistor uses the same epitaxial stack of semiconductor layers as the power field-effect transistor. That is, the power field-effect transistor includes a part of an epitaxial stack of semiconductor layers having a heterojunction between at least two adjacent semiconductor layers, and the sense field-effect transistor includes another part of this same epitaxial stack of semiconductor layers.

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