公开(公告)号：US09209038B2

公开(公告)日：2015-12-08

申请号：US14267959

申请日：2014-05-02

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Jason Richard Cantone ,  Linus Jang ,  Ryan Ryoung-Han Kim

IPC: H01L21/00 ,  H01L21/308 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L21/3086 ,  H01L21/823431

Abstract: Methods for fabricating integrated circuits and for forming masks for fabricating integrated circuits are provided. An exemplary method for fabricating an integrated circuit includes providing a patternable structure having first and second regions and including upper and lower mandrel layers. The method etches upper mandrels from the upper mandrel layer in the first and second regions. The method includes forming first upper spacer structures having a first width adjacent upper mandrels in the first region and forming second upper spacer structures having a second width not equal to the first width adjacent upper mandrels in the second region. The method etches the lower mandrel layer using the first and second upper spacer structures as an etch mask to form lower mandrels. Further, the method includes forming spacers adjacent the lower mandrels and etching a material using the spacers as an etch mask to form variably spaced features.

Abstract translation: 提供了制造集成电路和形成用于制造集成电路的掩模的方法。 一种用于制造集成电路的示例性方法包括提供具有第一和第二区域并且包括上部和下部心轴层的可图案化结构。 该方法在第一和第二区域中从上心轴层蚀刻上心轴。 该方法包括形成在第一区域中具有与上心轴相邻的第一宽度的第一上间隔结构，并且形成第二上间隔结构，其具有不等于第二区中相邻上心轴的第一宽度的第二宽度。 该方法使用第一和第二上间隔结构蚀刻下心轴层作为蚀刻掩模以形成下心轴。 此外，该方法包括形成邻近下心轴的间隔物，并使用间隔物蚀刻材料作为蚀刻掩模以形成可变间隔的特征。

公开(公告)号：US09209037B2

公开(公告)日：2015-12-08

申请号：US14196931

申请日：2014-03-04

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Jason Richard Cantone ,  Linus Jang ,  Jin Cho ,  Ryan Ryoung-Han Kim

IPC: H01L21/311 ,  H01L21/308

CPC classification number: H01L21/3086 ,  H01L21/3085 ,  H01L21/823431 ,  H01L21/845

Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming fin structures in a selected area of a semiconductor substrate. The method includes covering the fin structures and the semiconductor substrate with a mask and forming a trench in the mask to define no more than two exposed fin structures in the selected area. Further, the method includes removing the exposed fin structures to provide the selected area with a desired number of fin structures.

Abstract translation: 提供了制造集成电路的方法。 在一个实施例中，制造集成电路的方法包括在半导体衬底的选定区域中形成鳍结构。 该方法包括用掩模覆盖翅片结构和半导体衬底，并在掩模中形成沟槽，以在所选择的区域中限定不超过两个暴露的翅片结构。 此外，该方法包括去除暴露的翅片结构以向选定区域提供所需数量的翅片结构。

公开(公告)号：US20150255299A1

公开(公告)日：2015-09-10

申请号：US14196931

申请日：2014-03-04

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Jason Richard Cantone ,  Linus Jang ,  Jin Cho ,  Ryan Ryoung-Han Kim

IPC: H01L21/308

CPC classification number: H01L21/3086 ,  H01L21/3085 ,  H01L21/823431 ,  H01L21/845

Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming fin structures in a selected area of a semiconductor substrate. The method includes covering the fin structures and the semiconductor substrate with a mask and forming a trench in the mask to define no more than two exposed fin structures in the selected area. Further, the method includes removing the exposed fin structures to provide the selected area with a desired number of fin structures.

Abstract translation: 提供了制造集成电路的方法。 在一个实施例中，制造集成电路的方法包括在半导体衬底的选定区域中形成鳍结构。 该方法包括用掩模覆盖翅片结构和半导体衬底，并在掩模中形成沟槽，以在所选择的区域中限定不超过两个暴露的翅片结构。 此外，该方法包括去除暴露的翅片结构以向选定区域提供所需数量的翅片结构。

公开(公告)号：US20150318181A1

公开(公告)日：2015-11-05

申请号：US14267959

申请日：2014-05-02

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Jason Richard Cantone ,  Linus Jang ,  Ryan Ryoung-Han Kim

IPC: H01L21/308 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L21/3086 ,  H01L21/823431

Abstract: Methods for fabricating integrated circuits and for forming masks for fabricating integrated circuits are provided. An exemplary method for fabricating an integrated circuit includes providing a patternable structure having first and second regions and including upper and lower mandrel layers. The method etches upper mandrels from the upper mandrel layer in the first and second regions. The method includes forming first upper spacer structures having a first width adjacent upper mandrels in the first region and forming second upper spacer structures having a second width not equal to the first width adjacent upper mandrels in the second region. The method etches the lower mandrel layer using the first and second upper spacer structures as an etch mask to form lower mandrels. Further, the method includes forming spacers adjacent the lower mandrels and etching a material using the spacers as an etch mask to form variably spaced features.

Abstract translation: 提供了制造集成电路和形成用于制造集成电路的掩模的方法。 一种用于制造集成电路的示例性方法包括提供具有第一和第二区域并且包括上部和下部心轴层的可图案化结构。 该方法在第一和第二区域中从上心轴层蚀刻上心轴。 该方法包括形成在第一区域中具有与上心轴相邻的第一宽度的第一上间隔结构，并且形成第二上间隔结构，其具有不等于第二区中相邻上心轴的第一宽度的第二宽度。 该方法使用第一和第二上间隔结构蚀刻下心轴层作为蚀刻掩模以形成下心轴。 此外，该方法包括形成邻近下心轴的间隔物，并使用间隔物蚀刻材料作为蚀刻掩模以形成可变间隔的特征。