公开(公告)号：US20160172432A1

公开(公告)日：2016-06-16

申请号：US14699083

申请日：2015-04-29

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ki Young Lee ,  Sanggil Bae ,  Tony Joung

IPC: H01L49/02 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L28/60 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/5223 ,  H01L23/5225 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming a capacitor trench through a dielectric layer, and forming a base layer overlying the dielectric layer and within the capacitor trench. A base layer via gap is formed in the base layer, where the base layer via gap is positioned overlying the dielectric layer and the first contact. A base plate and a shield are formed from the base layer, where the base plate is within the capacitor trench. A capacitor insulating layer is formed overlying the base plate, the base layer, and within the base layer via gap, and a via is formed through the base layer via gap. A second contact and a top plate are simultaneously formed, where the second contact is formed in the via and the top plate is formed in the capacitor trench.

Abstract translation: 提供了集成电路及其制造方法。 一种用于制造集成电路的方法包括：通过电介质层形成电容器沟槽，以及形成覆盖介电层和电容器沟槽内的基极层。 基底层通孔间隙形成在基底层中，其中基底层通孔间隙位于覆盖电介质层和第一接触部分上。 从基底层形成基板和屏蔽层，其中基板在电容器沟槽内。 通过间隙，在基板，基底层和基底层之间形成电容器绝缘层，并且通过间隙通过基底层形成通孔。 同时形成第二接触和顶板，其中第二接触形成在通孔中，顶板形成在电容器沟槽中。

公开(公告)号：US20140159199A1

公开(公告)日：2014-06-12

申请号：US13712234

申请日：2012-12-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ki Young Lee ,  Sanggil Bae ,  Tony Joung

IPC: H01L49/02

CPC classification number: H01L29/66181 ,  H01L28/60 ,  H01L29/94

Abstract: A serial capacitor comprised of a bottom electrode, a top electrode that is conductively coupled the bottom electrode, a middle electrode positioned between the bottom and top electrode, a lower dielectric layer positioned between the bottom and middle electrodes, and an upper dielectric layer positioned between the middle and the electrodes. A method includes forming the bottom electrode in a first layer of insulating material, forming the lower dielectric layer and the middle electrode above the bottom electrode, wherein the middle electrode is positioned in a second layer of insulating material, forming the upper dielectric layer above the middle electrode, forming an opening that exposes a portion of the bottom electrode, and forming the top electrode above the upper dielectric layer, wherein a portion of the top electrode extends through the opening and contacts the bottom electrode.

Abstract translation: 一种串联电容器，包括底部电极，导电耦合底部电极的顶部电极，位于底部和顶部电极之间的中间电极，位于底部和中间电极之间的下部电介质层，以及位于 中间和电极。 一种方法包括在第一绝缘材料层中形成底部电极，在底部电极之上形成下部电介质层和中间电极，其中中间电极位于第二绝缘材料层中，形成上部电介质层 中间电极，形成露出所述底部电极的一部分的开口，以及在所述上部电介质层的上方形成所述顶部电极，其中所述顶部电极的一部分延伸穿过所述开口并接触所述底部电极。

公开(公告)号：US09349787B1

公开(公告)日：2016-05-24

申请号：US14699083

申请日：2015-04-29

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ki Young Lee ,  Sanggil Bae ,  Tony Joung

IPC: H01L21/768 ,  H01L23/522 ,  H01L49/02

CPC classification number: H01L28/60 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/5223 ,  H01L23/5225 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming a capacitor trench through a dielectric layer, and forming a base layer overlying the dielectric layer and within the capacitor trench. A base layer via gap is formed in the base layer, where the base layer via gap is positioned overlying the dielectric layer and the first contact. A base plate and a shield are formed from the base layer, where the base plate is within the capacitor trench. A capacitor insulating layer is formed overlying the base plate, the base layer, and within the base layer via gap, and a via is formed through the base layer via gap. A second contact and a top plate are simultaneously formed, where the second contact is formed in the via and the top plate is formed in the capacitor trench.

Abstract translation: 提供了集成电路及其制造方法。 一种用于制造集成电路的方法包括：通过电介质层形成电容器沟槽，以及形成覆盖介电层和电容器沟槽内的基极层。 基底层通孔间隙形成在基底层中，其中基底层通孔间隙位于覆盖电介质层和第一接触部分上。 从基底层形成基板和屏蔽层，其中基板在电容器沟槽内。 通过间隙，在基板，基底层和基底层之间形成电容器绝缘层，并且通过间隙通过基底层形成通孔。 同时形成第二接触和顶板，其中第二接触形成在通孔中，顶板形成在电容器沟槽中。

公开(公告)号：US09373680B1

公开(公告)日：2016-06-21

申请号：US14611908

申请日：2015-02-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ki Young Lee ,  Tony Joung ,  Sanggil Bae

IPC: H01L21/02 ,  H01L49/02 ,  H01L23/522 ,  H01L21/768 ,  H01L21/311 ,  H01L23/532 ,  H01L27/08

CPC classification number: H01L28/40 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76831 ,  H01L23/5223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L27/0805 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits with MIM capacitors and methods for producing them with metal and oxide hard masks are provided. Embodiments include disposing a dielectric layer over an ILD, the ILD including a contact therethrough in a first region; forming a capacitor trench in the dielectric layer in a second region; forming a MIM hard mask by: disposing a first metal hard mask in the first region and in the capacitor trench in the second region; disposing an oxide hard mask over the first metal hard mask; and disposing a second metal hard mask over the oxide hard mask; forming a metal line trench through the MIM hard mask in the first region, including over the contact, while masking the second region; and removing portions of the MIM hard mask in the capacitor trench, wherein a remaining portion of the first metal hard mask comprises a bottom plate of an MIM capacitor.

Abstract translation: 提供具有MIM电容器的集成电路和用金属和氧化物硬掩模制造它们的方法。 实施例包括在ILD上设置介电层，ILD在第一区域中包括穿过其中的接触; 在第二区域中在所述电介质层中形成电容器沟槽; 通过以下方式形成MIM硬掩模：在第一区域和第二区域的电容器沟槽中设置第一金属硬掩模; 在第一金属硬掩模上设置氧化物硬掩模; 并在所述氧化物硬掩模上设置第二金属硬掩模; 在所述第一区域中形成穿过所述MIM硬掩模的金属线沟槽，包括在所述接触件上方，同时掩蔽所述第二区域; 以及去除所述电容器沟槽中的MIM硬掩模的部分，其中所述第一金属硬掩模的剩余部分包括MIM电容器的底板。

公开(公告)号：US08809149B2

公开(公告)日：2014-08-19

申请号：US13712234

申请日：2012-12-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ki Young Lee ,  Sanggil Bae ,  Tony Joung

IPC: H01L21/336 ,  H01L29/788

CPC classification number: H01L29/66181 ,  H01L28/60 ,  H01L29/94

Abstract: A serial capacitor comprised of a bottom electrode, a top electrode that is conductively coupled the bottom electrode, a middle electrode positioned between the bottom and top electrode, a lower dielectric layer positioned between the bottom and middle electrodes, and an upper dielectric layer positioned between the middle and the electrodes. A method includes forming the bottom electrode in a first layer of insulating material, forming the lower dielectric layer and the middle electrode above the bottom electrode, wherein the middle electrode is positioned in a second layer of insulating material, forming the upper dielectric layer above the middle electrode, forming an opening that exposes a portion of the bottom electrode, and forming the top electrode above the upper dielectric layer, wherein a portion of the top electrode extends through the opening and contacts the bottom electrode.

Abstract translation: 一种串联电容器，包括底部电极，导电耦合底部电极的顶部电极，位于底部和顶部电极之间的中间电极，位于底部和中间电极之间的下部电介质层，以及位于 中间和电极。 一种方法包括在第一绝缘材料层中形成底部电极，在底部电极之上形成下部电介质层和中间电极，其中中间电极位于第二绝缘材料层中，形成上部电介质层 中间电极，形成露出所述底部电极的一部分的开口，以及在所述上部电介质层的上方形成所述顶部电极，其中所述顶部电极的一部分延伸穿过所述开口并接触所述底部电极。