公开(公告)号：US20180019241A1

公开(公告)日：2018-01-18

申请号：US15208495

申请日：2016-07-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： David Paul Brunco ,  Jeffrey Bowman Johnson

IPC: H01L27/092 ,  H01L29/10 ,  H01L21/225 ,  H01L21/02 ,  H01L21/762 ,  H01L21/265 ,  H01L29/167 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/02529 ,  H01L21/2251 ,  H01L21/26513 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/823892 ,  H01L29/1033 ,  H01L29/1083 ,  H01L29/167

Abstract: Generally, in one embodiment, the present disclosure is directed to a method for forming a transistor. The method includes: implanting a substrate to form at least one of an n and p doped region; depositing an epitaxial semiconductor layer over the substrate; forming trenches through the epitaxial layer and partially through at least one of an n and p doped region; forming dielectric isolation regions in the trenches; forming a fin in an upper portion of the epitaxial semiconductor layer by partially recessing the dielectric isolation regions; forming a gate dielectric adjacent at least two surfaces of the fin; and diffusing dopant from at least one of the n and p doped regions at least partially into the epitaxial semiconductor layer to form a diffusion doped transition region adjacent a bottom portion of the fin.

公开(公告)号：US10325913B2

公开(公告)日：2019-06-18

申请号：US15875609

申请日：2018-01-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： David Paul Brunco ,  Jeffrey Bowman Johnson

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/225 ,  H01L21/265 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/167 ,  H01L21/22

Abstract: Generally, in one embodiment, the present disclosure is directed to a method for forming a transistor. The method includes: implanting a substrate to form at least one of an n and p doped region; depositing an epitaxial semiconductor layer over the substrate; forming trenches through the epitaxial layer and partially through at least one of an n and p doped region; forming dielectric isolation regions in the trenches; forming a fin in an upper portion of the epitaxial semiconductor layer by partially recessing the dielectric isolation regions; forming a gate dielectric adjacent at least two surfaces of the fin; and diffusing dopant from at least one of the n and p doped regions at least partially into the epitaxial semiconductor layer to form a diffusion doped transition region adjacent a bottom portion of the fin.

公开(公告)号：US20180145079A1

公开(公告)日：2018-05-24

申请号：US15875609

申请日：2018-01-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： David Paul Brunco ,  Jeffrey Bowman Johnson

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/225 ,  H01L21/265 ,  H01L21/762 ,  H01L21/02 ,  H01L29/167 ,  H01L29/10

CPC classification number: H01L27/0924 ,  H01L21/02529 ,  H01L21/22 ,  H01L21/2251 ,  H01L21/26513 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/823892 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/167

Abstract: Generally, in one embodiment, the present disclosure is directed to a method for forming a transistor. The method includes: implanting a substrate to form at least one of an n and p doped region; depositing an epitaxial semiconductor layer over the substrate; forming trenches through the epitaxial layer and partially through at least one of an n and p doped region; forming dielectric isolation regions in the trenches; forming a fin in an upper portion of the epitaxial semiconductor layer by partially recessing the dielectric isolation regions; forming a gate dielectric adjacent at least two surfaces of the fin; and diffusing dopant from at least one of the n and p doped regions at least partially into the epitaxial semiconductor layer to form a diffusion doped transition region adjacent a bottom portion of the fin.

公开(公告)号：US09911740B2

公开(公告)日：2018-03-06

申请号：US15208495

申请日：2016-07-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： David Paul Brunco ,  Jeffrey Bowman Johnson

IPC: H01L27/088 ,  H01L27/092 ,  H01L21/265 ,  H01L21/762 ,  H01L21/225 ,  H01L21/02 ,  H01L29/167 ,  H01L21/8238 ,  H01L29/10

CPC classification number: H01L27/0924 ,  H01L21/02529 ,  H01L21/2251 ,  H01L21/26513 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/823892 ,  H01L29/1033 ,  H01L29/1083 ,  H01L29/167

Abstract: Generally, in one embodiment, the present disclosure is directed to a method for forming a transistor. The method includes: implanting a substrate to form at least one of an n and p doped region; depositing an epitaxial semiconductor layer over the substrate; forming trenches through the epitaxial layer and partially through at least one of an n and p doped region; forming dielectric isolation regions in the trenches; forming a fin in an upper portion of the epitaxial semiconductor layer by partially recessing the dielectric isolation regions; forming a gate dielectric adjacent at least two surfaces of the fin; and diffusing dopant from at least one of the n and p doped regions at least partially into the epitaxial semiconductor layer to form a diffusion doped transition region adjacent a bottom portion of the fin.