公开(公告)号：US20180145079A1

公开(公告)日：2018-05-24

申请号：US15875609

申请日：2018-01-19

申请人： GLOBALFOUNDRIES INC.

发明人： David Paul Brunco ,  Jeffrey Bowman Johnson

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L21/225 ,  H01L21/265 ,  H01L21/762 ,  H01L21/02 ,  H01L29/167 ,  H01L29/10

CPC分类号： H01L27/0924 ,  H01L21/02529 ,  H01L21/22 ,  H01L21/2251 ,  H01L21/26513 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/823892 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/167

摘要： Generally, in one embodiment, the present disclosure is directed to a method for forming a transistor. The method includes: implanting a substrate to form at least one of an n and p doped region; depositing an epitaxial semiconductor layer over the substrate; forming trenches through the epitaxial layer and partially through at least one of an n and p doped region; forming dielectric isolation regions in the trenches; forming a fin in an upper portion of the epitaxial semiconductor layer by partially recessing the dielectric isolation regions; forming a gate dielectric adjacent at least two surfaces of the fin; and diffusing dopant from at least one of the n and p doped regions at least partially into the epitaxial semiconductor layer to form a diffusion doped transition region adjacent a bottom portion of the fin.

公开(公告)号：US20150318169A1

公开(公告)日：2015-11-05

申请号：US14267634

申请日：2014-05-01

申请人： GLOBALFOUNDRIES Inc.

发明人： Yi Qi ,  Ajey Poovannummoottil Jacob ,  Jody A. Fronheiser ,  Murat Kerem Akarvardar ,  David Paul Brunco

IPC分类号： H01L21/02 ,  H01L29/161 ,  H01L29/66

CPC分类号： H01L29/161 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7848

摘要： One illustrative method disclosed herein includes, among other things, forming a fin in a semiconductor substrate and performing an epitaxial deposition process using a combination of silane (SiH4), dichlorosilane (SiH2Cl2), germane (GeH4) and a carrier gas to form an epi semiconductor material around the fin, wherein the flow rate of dichlorosilane used during the epitaxial deposition process is equal to 10-90% of the combined flow rate of silane and dichlorosilane.

摘要翻译： 本文公开的一种说明性方法包括在半导体衬底中形成翅片并使用硅烷（SiH 4），二氯硅烷（SiH 2 Cl 2），锗烷（GeH 4）和载气的组合进行外延沉积工艺以形成外延 散热片周围的半导体材料，其中在外延沉积工艺期间使用的二氯硅烷的流速等于硅烷和二氯硅烷的组合流速的10-90％。

公开(公告)号：US10014409B1

公开(公告)日：2018-07-03

申请号：US15393400

申请日：2016-12-29

申请人： GLOBALFOUNDRIES INC.

发明人： Xusheng Wu ,  David Paul Brunco

IPC分类号： H01L29/732 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L29/08 ,  H01L29/06

摘要： A vertical fin field effect transistor includes a semiconductor fin disposed over a well region and a gate conductor layer disposed over a sidewall of the fin, and extending laterally over a top surface of the well region adjacent to the fin. The extension of the gate conductor over the bottom source/drain effectively increases the channel length of the vertical FinFET device independent of the fin height. A bottom source/drain region is laterally adjacent to the well region such that the portion of the well region covered by the laterally extended gate stack is between the bottom source/drain region and the portion of the well region immediately under the fin. A top source/drain region is located above the fin. The device is operated in circuits by use of electrical contacts to the bottom source/drain, the gate conductor, and the top source/drain.

公开(公告)号：US20170250183A1

公开(公告)日：2017-08-31

申请号：US15053984

申请日：2016-02-25

申请人： GLOBALFOUNDRIES INC.

发明人： David Paul Brunco

IPC分类号： H01L27/092 ,  H01L21/02 ,  H01L21/306 ,  H01L29/06 ,  H01L29/167 ,  H01L29/10 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/265

CPC分类号： H01L27/0924 ,  H01L21/02532 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/1095 ,  H01L29/167

摘要： At least one method, apparatus and system disclosed involves forming a finFET device having silicon and silicon germanium fins. The method includes: forming an n-doped and a p-doped region in a semiconductor wafer; forming a layer of silicon above both the those regions; removing a portion of the silicon layer above the p-doped region to create a first recess; forming a layer of silicon germanium in the first recess; etching away at least a portion of the silicon layer and the underlying p-doped region; etching away at least a portion of the silicon germanium layer and the underlying n-doped region; forming fins from the unetched silicon and silicon germanium layers; and forming a shallow trench isolation dielectric in the etched away portion of the silicon layer and the underlying p-doped region and in the etched away portion of the silicon germanium layer and the underlying n-doped region.

公开(公告)号：US20180102291A1

公开(公告)日：2018-04-12

申请号：US15288503

申请日：2016-10-07

申请人： GLOBALFOUNDRIES INC.

发明人： David Paul Brunco ,  Daniel Jaeger

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L21/02

CPC分类号： H01L21/823431 ,  H01L21/02129 ,  H01L21/823481 ,  H01L27/0886

摘要： Generally, the present disclosure is directed to a method for forming a FinFET device that may be used in designs that include both tight and relaxed fin pitches. The method for forming the fins includes: forming a first layer of doped silicate glass above a semiconductor wafer and within a plurality of recesses located adjacent the fins; forming a first layer of nitride above the first doped silicate glass layer; and forming a conformal oxide layer above the first nitride layer, substantially filling relatively narrow recesses between fins having a tight pitch and lining relatively wide recesses between fins having a relaxed pitch.

公开(公告)号：US09929159B2

公开(公告)日：2018-03-27

申请号：US15053984

申请日：2016-02-25

申请人： GLOBALFOUNDRIES INC.

发明人： David Paul Brunco

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/306 ,  H01L21/265 ,  H01L29/167 ,  H01L29/10 ,  H01L21/762 ,  H01L29/06

CPC分类号： H01L27/0924 ,  H01L21/02532 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/1095 ,  H01L29/167

摘要： At least one method, apparatus and system disclosed involves forming a finFET device having silicon and silicon germanium fins. The method includes: forming an n-doped and a p-doped region in a semiconductor wafer; forming a layer of silicon above both the those regions; removing a portion of the silicon layer above the p-doped region to create a first recess; forming a layer of silicon germanium in the first recess; etching away at least a portion of the silicon layer and the underlying p-doped region; etching away at least a portion of the silicon germanium layer and the underlying n-doped region; forming fins from the unetched silicon and silicon germanium layers; and forming a shallow trench isolation dielectric in the etched away portion of the silicon layer and the underlying p-doped region and in the etched away portion of the silicon germanium layer and the underlying n-doped region.

公开(公告)号：US20180019241A1

公开(公告)日：2018-01-18

申请号：US15208495

申请日：2016-07-12

申请人： GLOBALFOUNDRIES INC.

发明人： David Paul Brunco ,  Jeffrey Bowman Johnson

IPC分类号： H01L27/092 ,  H01L29/10 ,  H01L21/225 ,  H01L21/02 ,  H01L21/762 ,  H01L21/265 ,  H01L29/167 ,  H01L21/8238

CPC分类号： H01L27/0924 ,  H01L21/02529 ,  H01L21/2251 ,  H01L21/26513 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/823892 ,  H01L29/1033 ,  H01L29/1083 ,  H01L29/167

摘要： Generally, in one embodiment, the present disclosure is directed to a method for forming a transistor. The method includes: implanting a substrate to form at least one of an n and p doped region; depositing an epitaxial semiconductor layer over the substrate; forming trenches through the epitaxial layer and partially through at least one of an n and p doped region; forming dielectric isolation regions in the trenches; forming a fin in an upper portion of the epitaxial semiconductor layer by partially recessing the dielectric isolation regions; forming a gate dielectric adjacent at least two surfaces of the fin; and diffusing dopant from at least one of the n and p doped regions at least partially into the epitaxial semiconductor layer to form a diffusion doped transition region adjacent a bottom portion of the fin.

公开(公告)号：US10325913B2

公开(公告)日：2019-06-18

申请号：US15875609

申请日：2018-01-19

申请人： GLOBALFOUNDRIES INC.

发明人： David Paul Brunco ,  Jeffrey Bowman Johnson

IPC分类号： H01L27/092 ,  H01L21/02 ,  H01L21/225 ,  H01L21/265 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/167 ,  H01L21/22

摘要： Generally, in one embodiment, the present disclosure is directed to a method for forming a transistor. The method includes: implanting a substrate to form at least one of an n and p doped region; depositing an epitaxial semiconductor layer over the substrate; forming trenches through the epitaxial layer and partially through at least one of an n and p doped region; forming dielectric isolation regions in the trenches; forming a fin in an upper portion of the epitaxial semiconductor layer by partially recessing the dielectric isolation regions; forming a gate dielectric adjacent at least two surfaces of the fin; and diffusing dopant from at least one of the n and p doped regions at least partially into the epitaxial semiconductor layer to form a diffusion doped transition region adjacent a bottom portion of the fin.

公开(公告)号：US20160064472A1

公开(公告)日：2016-03-03

申请号：US14835278

申请日：2015-08-25

申请人： GLOBALFOUNDRIES, Inc.

发明人： Lili Cheng ,  Dina H. Triyoso ,  Jeasung Park ,  David Paul Brunco ,  Robert Fox ,  Sanford Chu

IPC分类号： H01L49/02 ,  G06F17/50 ,  H01L21/02 ,  H01L23/522 ,  H01L21/822

CPC分类号： H01L28/60 ,  G06F17/5068 ,  H01L21/02181 ,  H01L21/02189 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： Integrated circuits including a MIMCAP device and methods of forming the integrated circuits are provided. An exemplary method of forming an integrated circuit including a MIMCAP device includes pre-determining a thickness of at least one of a bottom high-K layer or a top high-K layer of the MIMCAP device, followed by fabricating the MIMCAP device. The pre-determined thickness is established based upon a pre-determined TDDB lifetime for the MIMCAP device and a minimum target capacitance density at an applied voltage bias to be employed for the MIMCAP device. The MIMCAP device includes a bottom electrode and a dielectric layer disposed over the bottom electrode. The dielectric layer includes a stack of individual layers including the bottom high-K layer, the top high-K layer, and a lower-K layer sandwiched therebetween. At least one of the bottom high-K layer or the top high-K layer has the pre-determined thickness.

摘要翻译： 提供了包括MIMCAP器件的集成电路和形成集成电路的方法。 形成包括MIMCAP器件的集成电路的示例性方法包括预先确定MIMCAP器件的底部高K层或顶部高K层中的至少之一的厚度，然后制造MIMCAP器件。 预先确定的厚度是基于MIMCAP器件的预定的TDDB寿命和MIMCAP器件所采用的施加电压偏置下的最小目标电容密度而建立的。 MIMCAP器件包括设置在底部电极上的底部电极和电介质层。 电介质层包括层叠的各层，包括底部高K层，顶部高K层和夹在其间的下部K层。 底部高K层或顶部高K层中的至少一层具有预定厚度。

公开(公告)号：US08963225B2

公开(公告)日：2015-02-24

申请号：US14024820

申请日：2013-09-12

申请人： IMEC ,  GLOBALFOUNDRIES Inc.

发明人： Benjamin Vincent ,  Geert Hellings ,  David Paul Brunco

IPC分类号： H01L29/94 ,  H01L21/336

CPC分类号： H01L29/66795 ,  H01L21/02532 ,  H01L21/0257 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/785 ,  H01L29/7856

摘要： The disclosure is related to a band engineered semiconductor device comprising a substrate, a protruding structure that is formed in a recess in the substrate and is extending above the recess having a buried portion and an extended portion, and wherein at least the extended portion comprises a semiconductor material having an inverted ‘V’ band gap profile with a band gap value increasing gradually from a first value at lateral edges of the structure to a second value, higher than the first value, in a center of the structure. The disclosure is also related to the method of manufacturing of such band engineered semiconductor device.

摘要翻译： 本发明涉及一种带状工程半导体器件，其包括衬底，突出结构，其形成在衬底中的凹部中并且在凹部上方延伸，具有掩埋部分和延伸部分，并且其中至少延伸部分包括 具有倒置“V”带隙分布的半导体材料，带隙值从该结构的横向边缘处的第一值逐渐增加到高于该结构的中心的第二值。 本发明还涉及这种带状工程半导体器件的制造方法。