公开(公告)号：US12084765B2

公开(公告)日：2024-09-10

申请号：US17590799

申请日：2022-02-01

Applicant: TOKYO ELECTRON LIMITED

Inventor： Reita Igarashi

IPC: C23C16/455 ,  H01L21/22

CPC classification number: C23C16/45548 ,  C23C16/45578 ,  H01L21/22

Abstract: A processing apparatus includes: a processing container; a first injector extending in a longitudinal direction along an inner wall of the processing container, wherein the first injector includes a first introduction port formed at a lower end and first gas holes formed in the extending portion; and a second injector extending upward along the inner wall of the processing container, folded back at an upper portion, and then extending downward, wherein the second injector includes a second introduction port formed at a lower end of an upward extending portion and second gas holes formed in a downward extending portion. The first injector includes a first throttle portion having a cross-sectional area decreasing as a distance from the first introduction port increases. The second injector includes a second throttle portion formed in the downward extending portion and having a cross-sectional area decreasing as a distance from the second introduction port increases.

公开(公告)号：US20230386906A1

公开(公告)日：2023-11-30

申请号：US18446521

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Chen Tseng ,  Sih-Hao Liao ,  Po-Han Wang ,  Yu-Hsiang Hu ,  Hung-Jui Kuo

IPC: H01L21/768 ,  H01L21/22 ,  H01L23/498 ,  H01L23/538 ,  H01L21/48 ,  H01L23/48

CPC classification number: H01L21/76822 ,  H01L21/22 ,  H01L21/76838 ,  H01L23/49822 ,  H01L23/49827 ,  H01L21/31144 ,  H01L23/49833 ,  H01L21/4857 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5389

Abstract: In an embodiment, a method includes: dispensing a first dielectric layer around and on a first metallization pattern, the first dielectric layer including a photoinsensitive molding compound; planarizing the first dielectric layer such that surfaces of the first dielectric layer and the first metallization pattern are planar; forming a second metallization pattern on the first dielectric layer and the first metallization pattern; dispensing a second dielectric layer around the second metallization pattern and on the first dielectric layer, the second dielectric layer including a photosensitive molding compound; patterning the second dielectric layer with openings exposing portions of the second metallization pattern; and forming a third metallization pattern on the second dielectric layer and in the openings extending through the second dielectric layer, the third metallization pattern coupled to the portions of the second metallization pattern exposed by the openings.

公开(公告)号：US11784048B2

公开(公告)日：2023-10-10

申请号：US17329117

申请日：2021-05-24

Applicant: AKHAN Semiconductor, Inc.

Inventor： Adam Khan

IPC: H01L21/04 ,  H01L29/66 ,  H01L29/868 ,  H01L29/16 ,  H01L21/22

CPC classification number: H01L21/0405 ,  H01L21/0415 ,  H01L21/22 ,  H01L29/1602 ,  H01L29/6603 ,  H01L29/868 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed herein is a new and improved system and method for fabricating diamond semiconductors. The system may include a diamond malarial having n-type donor atoms and a diamond lattice, wherein 0.16% of the donor atoms contribute conduction electrons with mobility greater than 770 cm2/Vs to the diamond lattice at 100 kPa and 300K. The method of fabricating diamond semiconductors may include the steps of selecting a diamond material having a diamond lattice; introducing a minimal amount of acceptor dopant atoms to the diamond lattice to create ion tracks; introducing substitutional dopant atoms to the diamond lattice through the ion tracks; and annealing the diamond lattice.

公开(公告)号：US11705334B2

公开(公告)日：2023-07-18

申请号：US17366260

申请日：2021-07-02

Applicant: KABUSHIKI KAISHA TOSHIBA ,  TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION

Inventor： Yuhki Fujino

IPC: H01L29/78 ,  H01L21/22 ,  H01L21/285 ,  H01L21/265 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L21/324

CPC classification number: H01L21/22 ,  H01L21/265 ,  H01L21/28556 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/6659

Abstract: A semiconductor device includes a semiconductor part; first and second electrodes, the semiconductor part being provided between the first and second electrodes; a control electrode selectively provided between the semiconductor part and the second electrode; and a contacting part electrically connecting the semiconductor part and the second electrode. The semiconductor part includes a first layer of a first conductivity type, a second layer of a second conductivity type provided between the first layer and the second electrode, a third layer of the first conductivity type selectively provided between the second layer and the second electrode, and a fourth layer of the second conductivity type selectively provided between the second layer and the second electrode. The contacting part includes a first semiconductor portion of the first conductivity type contacting the third layer, and a second semiconductor portion of the second conductivity type contacting the fourth layer.

公开(公告)号：US20190198632A1

公开(公告)日：2019-06-27

申请号：US16189247

申请日：2018-11-13

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takao KAMOSHIMA ,  Mitsuhiro ONUMA ,  Hiroaki OSAKA

IPC: H01L29/423 ,  H01L29/792 ,  H01L29/66 ,  H01L29/08 ,  H01L29/51 ,  H01L21/28 ,  H01L21/22 ,  H01L21/768

CPC classification number: H01L29/42344 ,  H01L21/22 ,  H01L21/28282 ,  H01L21/76897 ,  H01L29/0847 ,  H01L29/517 ,  H01L29/66833 ,  H01L29/7833 ,  H01L29/792

Abstract: To provide a semiconductor device capable of preventing short circuit between first and second gate electrodes. The semiconductor device has a semiconductor substrate, gate insulating film, first gate electrode, stacked film, and second gate electrode. The semiconductor substrate has a first surface including a first region and a second region adjacent thereto. The gate insulating film is placed on the semiconductor substrate in the first region. The first gate electrode is placed on the gate insulating film and has a side surface. The stacked film has a first oxide film on the second region and on the side surface of the first gate electrode, a nitride film on the first oxide film, and a second oxide film on the nitride film. The second gate electrode is placed on the stacked film in the second region. The side surface above the second gate electrode includes a protrusion toward the side of the second gate electrode.

公开(公告)号：US10056273B2

公开(公告)日：2018-08-21

申请号：US15696213

申请日：2017-09-06

Applicant: CANON ANELVA CORPORATION

Inventor： Masao Sasaki ,  Kazutoshi Yoshibayashi ,  Kenji Sato ,  Kenzou Murata

IPC: H01L21/67 ,  H05B3/24 ,  H01L21/324 ,  H01L21/22

CPC classification number: H01L21/67098 ,  H01L21/046 ,  H01L21/22 ,  H01L21/324 ,  H01L21/67109 ,  H05B3/145 ,  H05B3/24

Abstract: A heating apparatus includes a heater, an electron reflection plate, a filament arranged between the heater and the electron reflection plate, a heating power supply configured to supply an AC voltage between a first terminal and a second terminal of the filament to emit thermoelectrons from the filament, an acceleration power supply configured to supply an acceleration voltage between the filament and the heater, and a resistor arranged so as to form a path which connects the electron reflection plate and the heating power supply.

公开(公告)号：US20180190814A1

公开(公告)日：2018-07-05

申请号：US15394636

申请日：2016-12-29

Applicant: Texas Instruments Incorporated

Inventor： Sameer Pendharkar ,  Guru Mathur

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/49 ,  H01L29/06 ,  H01L29/66 ,  H01L21/22 ,  H01L21/28

CPC classification number: H01L29/7816 ,  H01L21/22 ,  H01L21/28035 ,  H01L23/528 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/0882 ,  H01L29/0886 ,  H01L29/1033 ,  H01L29/4238 ,  H01L29/4916 ,  H01L29/66681

Abstract: An integrated circuit includes a power transistor having at least one transistor finger that lies within a semiconductor material substrate. Each transistor finger has a source region stripe and a substantially parallel drain region stripe. A gate structure lies between the source region stripe and the drain region stripe and has a plurality of fingers that extend over the source region stripe. Contacts are formed that connect to the fingers of the gate structure over thick oxide islands in the source region stripes. A conductive gate runner is connected to the contacts of the gate layer structure over the thick oxide islands in the source region stripe.

公开(公告)号：US20180179625A1

公开(公告)日：2018-06-28

申请号：US15852668

申请日：2017-12-22

Applicant: TOKYO ELECTRON LIMITED

Inventor： Satoshi TAKAGI ,  Katsuhiko KOMORI ,  Mitsuhiro OKADA ,  Masahisa WATANABE ,  Kazuya TAKAHASHI ,  Kazuki YANO ,  Keisuke FUJITA

IPC: C23C16/24 ,  H01L21/22 ,  H01L21/205 ,  H01L21/3205 ,  H01L21/285 ,  C23C16/455

CPC classification number: C23C16/24 ,  C23C16/45544 ,  C23C16/45546 ,  C23C16/46 ,  H01L21/205 ,  H01L21/22 ,  H01L21/28562 ,  H01L21/32051 ,  H01L21/67017 ,  H01L21/67103 ,  H01L21/67109 ,  H01L21/67248 ,  H01L21/67303

Abstract: There is provided a film forming apparatus for performing a film forming process on substrates by heating the substrates while the substrates are held in a shelf shape by a substrate holder in a vertical reaction container. The film forming apparatus includes: an exhaust part configured to evacuate the reaction container; a gas supply part configured to supply a film forming gas into the reaction container; a heat insulating member provided above or below an arrangement region of the substrates to overlap with the arrangement region and configured to thermally insulate the arrangement region from an upper region above the arrangement region or a lower region below the arrangement region; and a through-hole provided in the heat insulating member at a position overlapping with central portions of the substrates to adjust a temperature distribution in a plane of each substrate held near the heat insulating member.

公开(公告)号：US20180164683A1

公开(公告)日：2018-06-14

申请号：US15567822

申请日：2016-04-20

Applicant: TORAY INDUSTRIES, INC.

Inventor： Takenori Fujiwara ,  Yugo Tanigaki

IPC: G03F7/038 ,  G03F7/039 ,  C08F212/14 ,  C08G73/10 ,  G03F7/16 ,  G03F7/20 ,  G03F7/32 ,  H01L21/308 ,  H01L21/3205 ,  H01L21/22

CPC classification number: G03F7/0387 ,  C08F212/14 ,  C08G73/1071 ,  C08L79/04 ,  C08L79/08 ,  G03F7/0046 ,  G03F7/0233 ,  G03F7/039 ,  G03F7/162 ,  G03F7/168 ,  G03F7/20 ,  G03F7/322 ,  G03F7/40 ,  H01L21/22 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/32051

Abstract: Provided is a resin composition including: (A1) an alkali-soluble resin having a specific structural unit; (A2) at least one resin selected from the group consisting of polyimides, polybenzoxazoles, polyamideimides, precursors thereof, and copolymers thereof, the resin having a substituent that reacts with a reactive group of the alkali-soluble resin; and (B) a photosensitizer, in which the amount of the resin (A2) is 310 to 2,000 parts by weight with respect to 100 parts by weight of the resin (A1).

公开(公告)号：US20180068853A1

公开(公告)日：2018-03-08

申请号：US15706751

申请日：2017-09-17

Applicant: Adam Khan

Inventor： Adam Khan

IPC: H01L21/04 ,  H01L21/22 ,  H01L29/868 ,  H01L29/66 ,  H01L29/16

CPC classification number: H01L21/0405 ,  H01L21/0415 ,  H01L21/22 ,  H01L29/1602 ,  H01L29/6603 ,  H01L29/868 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed herein is a new and improved system and method for fabricating diamond semiconductors. The system may include a diamond material having n-type donor atoms and a diamond lattice, wherein 0.16% of the donor atoms contribute conduction electrons with mobility greater than 770 cm2/Vs to the diamond lattice at 100 kPa and 300K. The method of fabricating diamond semiconductors may include the steps of selecting a diamond material having a diamond lattice; introducing a minimal amount of acceptor dopant atoms to the diamond lattice to create ion tracks; introducing substitutional dopant atoms to the diamond lattice through the ion tracks; and annealing the diamond lattice.