Frequency-locked voltage regulated loop
    1.
    发明授权
    Frequency-locked voltage regulated loop 有权
    频率锁定电压调节回路

    公开(公告)号:US09503106B1

    公开(公告)日:2016-11-22

    申请号:US14966881

    申请日:2015-12-11

    CPC classification number: H03L7/06 H03L7/00

    Abstract: An integrated circuit includes a frequency-locked voltage regulated loop that further includes a voltage controlled oscillator (VCO), a frequency divider that generates sequential timing signals based on a period of the VCO from a frequency divided VCO signal, a frequency-to-voltage converter (FVC) that converts the frequency divided VCO signal into an output voltage, FVCOUT, an internal reference voltage, and a voltage regulator that generates a control voltage, VCOIN, that is fed back to the VCO to lock a frequency of the VCO in the frequency-locked voltage regulated loop.

    Abstract translation: 集成电路包括频率锁定电压调节环路,其进一步包括压控振荡器(VCO),分频器,其基于来自频分压VCO信号的VCO的周期产生顺序定时信号,频率 - 电压 转换器(FVC),其将分频的VCO信号转换为输出电压,FVCOUT,内部参考电压和产生控制电压的电压调节器VCOIN,VCOIN反馈到VCO以锁定VCO的频率 锁频电压调节回路。

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