公开(公告)号：US10438894B1

公开(公告)日：2019-10-08

申请号：US15993523

申请日：2018-05-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Mukta Farooq ,  Koushik Ramachandran ,  Eric Perfecto ,  Ian Melville

IPC: H01L23/495 ,  H01L23/538 ,  H01L23/498 ,  H01L25/065 ,  H01L23/00

Abstract: A multi-chip semiconductor device with multi-level structure including a substrate with a top substrate surface, a cavity with a depth in the substrate, a first chip having a top first chip surface with a first chip height, optionally including a second chip having a top second chip surface with a second chip height, and a connecting passive chip bridging the first chip, the second chip and the substrate by solder bumps wherein the solder bumps enable the connecting passive chip to be level.

公开(公告)号：US10409014B1

公开(公告)日：2019-09-10

申请号：US16031176

申请日：2018-07-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Koushik Ramachandran ,  Benjamin V. Fasano

IPC: G02B6/42

Abstract: A photonic integrated circuit (PIC) package includes a PIC die including electro-optical circuitry having an optical waveguide system therein and a V-groove fiber optic receptacle on a first surface thereof. The V-groove fiber optic receptacle positions an optical element, e.g., optical fiber(s), for optical coupling with the optical waveguide system. An optical element is operatively coupled to the optical waveguide system and positioned in the V-groove fiber optic receptacle. A magnetic force inducer (MFI) is positioned to forcibly direct the optical element into position in the V-groove fiber optic receptacle in response to application of a magnetic field from a direction opposite the V-groove fiber optic receptacle in the first surface. During assembly, a magnetic field may be applied to the MFI to generate the magnetic force. After adhering the optical element, the magnetic field may remain to allow the PIC package to be moved with more security. The MFI may remain with and become part of the finished assembly.

公开(公告)号：US10598860B2

公开(公告)日：2020-03-24

申请号：US15920537

申请日：2018-03-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Koushik Ramachandran ,  Benjamin V. Fasano ,  Edmund D. Blackshear

IPC: G02B6/30 ,  G02B6/38 ,  G02B6/44

Abstract: A photonic integrated circuit (PIC) fan-out package and related methods of forming same are disclosed. The PIC fan-out package includes: an overmold body; a PIC die in the overmold body, the PIC die including electro-optic circuitry; a plurality of optical fiber stubs operatively coupled to the electro-optic circuitry; an edge fiber coupling interface in a lateral side of the overmold body for coupling the plurality of optical fiber stubs to external optical fibers using a connector; an ancillary device in the overmold body; a redistribution wiring layer (RDL) interposer adjacent the overmold body and electrically connected to the PIC die and the ancillary device; and a ball grid array (BGA) electrically coupled to the PIC die and the ancillary device by the RDL interposer, the BGA configured to electrically couple the PIC die and the ancillary device to a printed circuit board (PCB).

公开(公告)号：US20190285804A1

公开(公告)日：2019-09-19

申请号：US15920537

申请日：2018-03-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Koushik Ramachandran ,  Benjamin V. Fasano ,  Edmund D. Blackshear

IPC: G02B6/30 ,  G02B6/44 ,  G02B6/38

Abstract: A photonic integrated circuit (PIC) fan-out package and related methods of forming same are disclosed. The PIC fan-out package includes: an overmold body; a PIC die in the overmold body, the PIC die including electro-optic circuitry; a plurality of optical fiber stubs operatively coupled to the electro-optic circuitry; an edge fiber coupling interface in a lateral side of the overmold body for coupling the plurality of optical fiber stubs to external optical fibers using a connector; an ancillary device in the overmold body; a redistribution wiring layer (RDL) interposer adjacent the overmold body and electrically connected to the PIC die and the ancillary device; and a ball grid array (BGA) electrically coupled to the PIC die and the ancillary device by the RDL interposer, the BGA configured to electrically couple the PIC die and the ancillary device to a printed circuit board (PCB).

公开(公告)号：US20180166356A1

公开(公告)日：2018-06-14

申请号：US15377496

申请日：2016-12-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shahid A. Butt ,  Koushik Ramachandran ,  Eric D. Perfecto

IPC: H01L23/367 ,  H01L23/373 ,  H01L23/498 ,  H01L21/48 ,  H01L21/78 ,  H01L23/00

Abstract: Various embodiments include integrated circuit (IC) package structures. In some cases, an IC package includes: a carrier having a recess; a plurality of IC chips coupled with the carrier inside the recess, the plurality of IC chips each including a plurality of connectors; a thermally conductive material between the plurality of IC chips and the carrier within the recess, the thermally conductive material coupling the plurality of IC chips with the carrier; a dielectric layer contacting the plurality of IC chips and the carrier; a redistribution layer (RDL) contacting the dielectric layer and the plurality of connectors, the RDL including a plurality of fan-out vias extending from the plurality of connectors and at least one connector coupling adjacent IC chips in the plurality of IC chips; and a set of solder balls contacting the RDL and connected with the plurality of fan-out vias.