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公开(公告)号:US10446442B2
公开(公告)日:2019-10-15
申请号:US15386097
申请日:2016-12-21
Applicant: GLOBALFOUNDRIES INC.
Inventor: Shahid A. Butt , Christopher L. Tessler
IPC: H01L21/683 , H01L21/768 , H01L23/48 , H01L23/66 , H01L21/84 , H01L27/12 , H01L29/78 , H01L49/02 , H01L29/40 , H01L23/367
Abstract: Disclosed are integrated circuit (IC) chip structures (e.g., radio frequency (RF) IC chip structures) and methods of forming the structures with an electrically insulative molding compound handler substrate. Each structure includes at least: an electrically insulative molding compound handler substrate; an insulator layer on the handler substrate; and one or more semiconductor devices (e.g., RF semiconductor devices) on the insulator layer. Each method includes at least: attaching a temporary carrier above back end of the line (BEOL) metal levels, which are over an interlayer dielectric layer covering one or more semiconductor devices; removing at least a portion of a semiconductor handler substrate, which is below the semiconductor device(s) and separated therefrom by an insulator layer; replacing the semiconductor handler substrate with a replacement handler substrate made of an electrically insulative molding compound; and removing the temporary carrier. The molding compound handler substrate provides backside isolation that prevents unwanted noise coupling.
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公开(公告)号:US20180166356A1
公开(公告)日:2018-06-14
申请号:US15377496
申请日:2016-12-13
Applicant: GLOBALFOUNDRIES INC.
Inventor: Shahid A. Butt , Koushik Ramachandran , Eric D. Perfecto
IPC: H01L23/367 , H01L23/373 , H01L23/498 , H01L21/48 , H01L21/78 , H01L23/00
Abstract: Various embodiments include integrated circuit (IC) package structures. In some cases, an IC package includes: a carrier having a recess; a plurality of IC chips coupled with the carrier inside the recess, the plurality of IC chips each including a plurality of connectors; a thermally conductive material between the plurality of IC chips and the carrier within the recess, the thermally conductive material coupling the plurality of IC chips with the carrier; a dielectric layer contacting the plurality of IC chips and the carrier; a redistribution layer (RDL) contacting the dielectric layer and the plurality of connectors, the RDL including a plurality of fan-out vias extending from the plurality of connectors and at least one connector coupling adjacent IC chips in the plurality of IC chips; and a set of solder balls contacting the RDL and connected with the plurality of fan-out vias.
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