公开(公告)号：US09607973B1

公开(公告)日：2017-03-28

申请号：US14946162

申请日：2015-11-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Benjamin V. Fasano ,  Michael S. Cranmer ,  Richard F. Indyk ,  Harry Cox ,  Katsuyuki Sakuma ,  Eric D. Perfecto

IPC: H01L21/44 ,  H01L25/18 ,  H01L25/00 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/5386 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/1146 ,  H01L2224/1184 ,  H01L2224/13017 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/16058 ,  H01L2224/16059 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/81191 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2224/81815 ,  H01L2924/014 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/157 ,  H01L2924/15717 ,  H01L2924/15738 ,  H01L2924/15788 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/00014

Abstract: A method of interconnecting first and second semiconductor dies is provided. A splice interposer is attached to a top surface of a substrate through first pillars formed on a bottom surface of the splice interposer. The first semiconductor die is attached to the top surface of a substrate through second pillars formed on a bottom surface of the first semiconductor die. The first semiconductor die is attached to a top surface of the splice interposer through third pillars formed on the bottom surface of the first semiconductor. The second semiconductor die is attached to the top surface of the splice interposer through fourth pillars formed on a bottom surface of the second semiconductor die. The first to fourth plurality of pillars and the splice interposer form interconnection and wiring between the first semiconductor die, the second semiconductor die and the substrate.

公开(公告)号：US10409014B1

公开(公告)日：2019-09-10

申请号：US16031176

申请日：2018-07-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Koushik Ramachandran ,  Benjamin V. Fasano

IPC: G02B6/42

Abstract: A photonic integrated circuit (PIC) package includes a PIC die including electro-optical circuitry having an optical waveguide system therein and a V-groove fiber optic receptacle on a first surface thereof. The V-groove fiber optic receptacle positions an optical element, e.g., optical fiber(s), for optical coupling with the optical waveguide system. An optical element is operatively coupled to the optical waveguide system and positioned in the V-groove fiber optic receptacle. A magnetic force inducer (MFI) is positioned to forcibly direct the optical element into position in the V-groove fiber optic receptacle in response to application of a magnetic field from a direction opposite the V-groove fiber optic receptacle in the first surface. During assembly, a magnetic field may be applied to the MFI to generate the magnetic force. After adhering the optical element, the magnetic field may remain to allow the PIC package to be moved with more security. The MFI may remain with and become part of the finished assembly.

公开(公告)号：US10002835B2

公开(公告)日：2018-06-19

申请号：US15427156

申请日：2017-02-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Benjamin V. Fasano ,  Michael S. Cranmer ,  Richard F. Indyk ,  Harry Cox ,  Katsuyuki Sakuma ,  Eric D. Perfecto

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L23/5386 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/1146 ,  H01L2224/1184 ,  H01L2224/13017 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/16058 ,  H01L2224/16059 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/81191 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2224/81815 ,  H01L2924/014 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/157 ,  H01L2924/15717 ,  H01L2924/15738 ,  H01L2924/15788 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/00014

Abstract: A semiconductor device and a stacked pillar used to interconnect a first semiconductor die and a second semiconductor die are provided. The semiconductor device has a substrate, a splice interposer, a first semiconductor die, a second semiconductor die and first to fourth plurality of pillars. The first to fourth plurality of pillars and the splice interposer form interconnection and wiring between the first semiconductor die, the second semiconductor die and the substrate. The stacked pillar has a first conductor layer formed on a surface of the first semiconductor die, a first solder layer formed on the first conductor layer, a second conductor layer formed on the first solder layer, and a second solder layer formed on the second conductor layer. The second solder layer is heat-reflowable to attach the stacked pillar to a surface of the second semiconductor.

公开(公告)号：US20190285804A1

公开(公告)日：2019-09-19

申请号：US15920537

申请日：2018-03-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Koushik Ramachandran ,  Benjamin V. Fasano ,  Edmund D. Blackshear

IPC: G02B6/30 ,  G02B6/44 ,  G02B6/38

Abstract: A photonic integrated circuit (PIC) fan-out package and related methods of forming same are disclosed. The PIC fan-out package includes: an overmold body; a PIC die in the overmold body, the PIC die including electro-optic circuitry; a plurality of optical fiber stubs operatively coupled to the electro-optic circuitry; an edge fiber coupling interface in a lateral side of the overmold body for coupling the plurality of optical fiber stubs to external optical fibers using a connector; an ancillary device in the overmold body; a redistribution wiring layer (RDL) interposer adjacent the overmold body and electrically connected to the PIC die and the ancillary device; and a ball grid array (BGA) electrically coupled to the PIC die and the ancillary device by the RDL interposer, the BGA configured to electrically couple the PIC die and the ancillary device to a printed circuit board (PCB).

公开(公告)号：US10598860B2

公开(公告)日：2020-03-24

申请号：US15920537

申请日：2018-03-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Koushik Ramachandran ,  Benjamin V. Fasano ,  Edmund D. Blackshear

IPC: G02B6/30 ,  G02B6/38 ,  G02B6/44

Abstract: A photonic integrated circuit (PIC) fan-out package and related methods of forming same are disclosed. The PIC fan-out package includes: an overmold body; a PIC die in the overmold body, the PIC die including electro-optic circuitry; a plurality of optical fiber stubs operatively coupled to the electro-optic circuitry; an edge fiber coupling interface in a lateral side of the overmold body for coupling the plurality of optical fiber stubs to external optical fibers using a connector; an ancillary device in the overmold body; a redistribution wiring layer (RDL) interposer adjacent the overmold body and electrically connected to the PIC die and the ancillary device; and a ball grid array (BGA) electrically coupled to the PIC die and the ancillary device by the RDL interposer, the BGA configured to electrically couple the PIC die and the ancillary device to a printed circuit board (PCB).