公开(公告)号：US20160218198A1

公开(公告)日：2016-07-28

申请号：US15092039

申请日：2016-04-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Veeraraghavan S. Basker ,  Krishna Iyengar ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/04 ,  H01L29/08

CPC classification number: H01L29/66795 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/7848 ,  H01L29/785

Abstract: After formation of a gate structure and a gate spacer, portions of an insulator layer underlying a semiconductor fin are etched to physically expose semiconductor surfaces of an underlying semiconductor material layer from underneath a source region and a drain region. Each of the extended source region and the extended drain region includes an anchored single crystalline semiconductor material portion that is in epitaxial alignment to the single crystalline semiconductor structure of the underlying semiconductor material layer and laterally applying a stress to the semiconductor fin. Because each anchored single crystalline semiconductor material portion is in epitaxial alignment with the underlying semiconductor material layer, the channel of the fin field effect transistor is effectively stressed along the lengthwise direction of the semiconductor fin.

公开(公告)号：US09349863B2

公开(公告)日：2016-05-24

申请号：US13961522

申请日：2013-08-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Veeraraghavan S. Basker ,  Krishna Iyengar ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC: H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/66795 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/7848 ,  H01L29/785

Abstract: After formation of a gate structure and a gate spacer, portions of an insulator layer underlying a semiconductor fin are etched to physically expose semiconductor surfaces of an underlying semiconductor material layer from underneath a source region and a drain region. Each of the extended source region and the extended drain region includes an anchored single crystalline semiconductor material portion that is in epitaxial alignment to the single crystalline semiconductor structure of the underlying semiconductor material layer and laterally applying a stress to the semiconductor fin. Because each anchored single crystalline semiconductor material portion is in epitaxial alignment with the underlying semiconductor material layer, the channel of the fin field effect transistor is effectively stressed along the lengthwise direction of the semiconductor fin.

Abstract translation: 在形成栅极结构和栅极间隔物之后，蚀刻半导体鳍片下面的绝缘体层的部分，以从源极区域和漏极区域下面物理地暴露下面的半导体材料层的半导体表面。 扩展源极区域和延伸漏极区域中的每一个包括锚定的单晶半导体材料部分，其与下面的半导体材料层的单晶半导体结构外延对准，并向半导体鳍片横向施加应力。 因为每个锚定的单晶半导体材料部分与下面的半导体材料层进行外延对准，所以鳍状场效应晶体管的沟道沿着半导体鳍片的长度方向被有效地应力。

公开(公告)号：US09991366B2

公开(公告)日：2018-06-05

申请号：US15092039

申请日：2016-04-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Veeraraghavan S. Basker ,  Krishna Iyengar ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L29/04 ,  H01L29/08

CPC classification number: H01L29/66795 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/7848 ,  H01L29/785

Abstract: After formation of a gate structure and a gate spacer, portions of an insulator layer underlying a semiconductor fin are etched to physically expose semiconductor surfaces of an underlying semiconductor material layer from underneath a source region and a drain region. Each of the extended source region and the extended drain region includes an anchored single crystalline semiconductor material portion that is in epitaxial alignment to the single crystalline semiconductor structure of the underlying semiconductor material layer and laterally applying a stress to the semiconductor fin. Because each anchored single crystalline semiconductor material portion is in epitaxial alignment with the underlying semiconductor material layer, the channel of the fin field effect transistor is effectively stressed along the lengthwise direction of the semiconductor fin.