公开(公告)号：US20170330834A1

公开(公告)日：2017-11-16

申请号：US15154367

申请日：2016-05-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Veeraraghavan S. Basker ,  Keith H. Tabakman ,  Patrick D. Carpenter ,  Guillaume Bouche ,  Michael V. Aquilino

IPC: H01L23/535 ,  H01L29/417 ,  H01L21/768 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L23/535 ,  H01L21/76816 ,  H01L21/76841 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a contact line being disposed within a dielectric layer and providing electrical connection to source/drain epitaxial regions surrounding a set of fins, the contact line including: a first portion of the contact line electrically isolated from a second portion of the contact line by a contact line spacer, wherein the first portion and the second portion each include a liner layer and a metal, the liner layer separating the metal from the dielectric layer and the source/drain epitaxial regions, and wherein the metal is directly in contact with the contact line spacer.

公开(公告)号：US20170301697A1

公开(公告)日：2017-10-19

申请号：US15098722

申请日：2016-04-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Alexander Reznicek ,  Veeraraghavan S. Basker ,  Shogo Mochizuki ,  Nicolas L. Breil ,  Oleg Gluschenkov

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/324 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3115

CPC classification number: H01L27/1211 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02623 ,  H01L21/31155 ,  H01L21/324 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/01 ,  H01L27/0886 ,  H01L29/161 ,  H01L29/6653 ,  H01L29/7848

Abstract: Relaxed silicon germanium fins are formed on a bulk silicon substrate through the lateral recrystallization of molten silicon germanium having high germanium content. Following formation of the silicon germanium fins, the silicon is selectively recessed.The resulting trenches are filled with electrically insulating material and then recessed down to the bottoms of the fins.

公开(公告)号：US20160247805A1

公开(公告)日：2016-08-25

申请号：US15144924

申请日：2016-05-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Veeraraghavan S. Basker ,  Andres Bryant ,  Tenko Yamashita

IPC: H01L27/092 ,  H01L29/417 ,  H01L29/06 ,  H01L27/12 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/45

CPC classification number: H01L27/0924 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/8238 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/823878 ,  H01L21/84 ,  H01L21/845 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/45

Abstract: In a method of forming a semiconductor structure, different sections of a dielectric layer are etched at different stages during processing to form a first gate sidewall spacer for a first FET (e.g., a NFET) and a second gate sidewall spacer for a second FET (e.g., a PFET) such that the first and second gate sidewall spacers are symmetric. Raised source/drain regions for the first FET are formed immediately following first gate sidewall spacer formation and raised source/drain regions for the second FET are formed immediately following second gate sidewall spacer formation. Since the gate sidewall spacers of the two FETs are symmetric, the source/drain junctions of the two FETs will also be symmetric. Additionally, due to an etch stop layer formed on the raised source/drain regions of the first FET, but not the second FET, different metal silicides on the raised source/drain regions of the different FETs.

Abstract translation: 在形成半导体结构的方法中，介电层的不同部分在处理期间在不同的阶段被蚀刻，以形成用于第一FET（例如，NFET）的第一栅极侧壁间隔件和用于第二FET的第二栅极侧壁间隔物 例如PFET），使得第一和第二栅极侧壁间隔物是对称的。 在第一栅极侧壁间隔物形成之后立即形成用于第一FET的升高的源极/漏极区，并且在第二栅极侧壁间隔物形成之后立即形成用于第二FET的升高的源极/漏极区。 由于两个FET的栅极侧壁间隔物是对称的，所以两个FET的源极/漏极结也将是对称的。 另外，由于形成在第一FET的升高的源极/漏极区上而不是第二FET的蚀刻停止层，不同的FET的升高的源极/漏极区上的不同的金属硅化物。

公开(公告)号：US20160218198A1

公开(公告)日：2016-07-28

申请号：US15092039

申请日：2016-04-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Veeraraghavan S. Basker ,  Krishna Iyengar ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/04 ,  H01L29/08

CPC classification number: H01L29/66795 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/7848 ,  H01L29/785

Abstract: After formation of a gate structure and a gate spacer, portions of an insulator layer underlying a semiconductor fin are etched to physically expose semiconductor surfaces of an underlying semiconductor material layer from underneath a source region and a drain region. Each of the extended source region and the extended drain region includes an anchored single crystalline semiconductor material portion that is in epitaxial alignment to the single crystalline semiconductor structure of the underlying semiconductor material layer and laterally applying a stress to the semiconductor fin. Because each anchored single crystalline semiconductor material portion is in epitaxial alignment with the underlying semiconductor material layer, the channel of the fin field effect transistor is effectively stressed along the lengthwise direction of the semiconductor fin.

公开(公告)号：US09337315B2

公开(公告)日：2016-05-10

申请号：US14157851

申请日：2014-01-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Bruce B. Doris ,  Johnathan E. Faltermeier

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/265 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/26586 ,  H01L21/823431 ,  H01L29/66803 ,  H01L29/785

Abstract: A FinFET having spacers with a substantially uniform profile along the length of a gate stack which covers a portion of a fin of semiconductor material formed on a substrate is provided by depositing spacer material conformally on both the fins and gate stack and performing an angled ion impurity implant approximately parallel to the gate stack to selectively cause damage to only spacer material deposited on the fin. Due to the damage caused by the angled implant, the spacer material on the fins can be etched with high selectivity to the spacer material on the gate stack.

公开(公告)号：US09960168B2

公开(公告)日：2018-05-01

申请号：US14582655

申请日：2014-12-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Benjamin Ryan Cipriany ,  Ramachandra Divakaruni ,  Brian J. Greene ,  Ali Khakifirooz ,  Byeong Yeol Kim ,  William Larsen Nicoll

IPC: H01L21/20 ,  H01L27/108 ,  H01L21/324 ,  H01L21/84 ,  H01L29/94 ,  H01L27/12 ,  H01L21/02 ,  H01L21/285 ,  H01L21/768

CPC classification number: H01L27/10829 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/28518 ,  H01L21/324 ,  H01L21/76895 ,  H01L21/845 ,  H01L27/10826 ,  H01L27/10867 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/945

Abstract: Structures and methods for deep trench capacitor connections are disclosed. The structure includes a reduced diameter top portion of the capacitor conductor. This increases the effective spacing between neighboring deep trench capacitors. Silicide or additional polysilicon are then deposited to complete the connection between the deep trench capacitor and a neighboring transistor.

公开(公告)号：US09680020B2

公开(公告)日：2017-06-13

申请号：US14794997

申请日：2015-07-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Veeraraghavan S. Basker ,  Chung-Hsun Lin ,  Zuoguang Liu ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/3065 ,  H01L29/417 ,  H01L29/08

CPC classification number: H01L29/7851 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848

Abstract: A method for forming fin field effect transistors includes epitaxially growing source and drain (S/D) regions on fins, the S/D regions including a diamond-shaped cross section and forming a dielectric liner over the S/D regions. A dielectric fill is etched over the S/D regions to expose a top portion of the diamond-shaped cross section. The fins are recessed into the diamond-shaped cross section. A top portion of the diamond-shaped cross section of the S/D regions is exposed. A contact liner is formed on the top portion of the diamond-shaped cross section of the S/D regions and in a recess where the fins were recessed. Contacts are formed over surfaces of the top portion and in the recess.

公开(公告)号：US09548306B2

公开(公告)日：2017-01-17

申请号：US15144924

申请日：2016-05-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Veeraraghavan S. Basker ,  Andres Bryant ,  Tenko Yamashita

IPC: H01L29/76 ,  H01L27/092 ,  H01L21/8238 ,  H01L27/12 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/45

CPC classification number: H01L27/0924 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/8238 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/823878 ,  H01L21/84 ,  H01L21/845 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/45

Abstract: In a method of forming a semiconductor structure, different sections of a dielectric layer are etched at different stages during processing to form a first gate sidewall spacer for a first FET (e.g., a NFET) and a second gate sidewall spacer for a second FET (e.g., a PFET) such that the first and second gate sidewall spacers are symmetric. Raised source/drain regions for the first FET are formed immediately following first gate sidewall spacer formation and raised source/drain regions for the second FET are formed immediately following second gate sidewall spacer formation. Since the gate sidewall spacers of the two FETs are symmetric, the source/drain junctions of the two FETs will also be symmetric. Additionally, due to an etch stop layer formed on the raised source/drain regions of the first FET, but not the second FET, different metal silicides on the raised source/drain regions of the different FETs.

Abstract translation: 在形成半导体结构的方法中，介电层的不同部分在处理期间在不同的阶段被蚀刻，以形成用于第一FET（例如，NFET）的第一栅极侧壁间隔件和用于第二FET的第二栅极侧壁间隔物 例如PFET），使得第一和第二栅极侧壁间隔物是对称的。 在第一栅极侧壁间隔物形成之后立即形成用于第一FET的升高的源极/漏极区，并且在第二栅极侧壁间隔物形成之后立即形成用于第二FET的升高的源极/漏极区。 由于两个FET的栅极侧壁间隔物是对称的，所以两个FET的源极/漏极结也将是对称的。 另外，由于形成在第一FET的升高的源极/漏极区上而不是第二FET的蚀刻停止层，不同的FET的升高的源极/漏极区上的不同的金属硅化物。

公开(公告)号：US20160268413A1

公开(公告)日：2016-09-15

申请号：US14641917

申请日：2015-03-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Veeraraghavan S. Basker ,  Eric C. T. Harley ,  Yue Ke ,  Alexander Reznicek ,  Henry K. Utomo

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/306 ,  H01L29/04 ,  H01L29/45 ,  H01L29/66 ,  H01L29/08

CPC classification number: H01L29/785 ,  H01L21/30604 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor structure includes a fin upon a semiconductor substrate. A clean epitaxial growth surface is provided by forming a buffer layer upon fin sidewalls and an upper surface of the fin. The buffer layer may be epitaxially grown. Diamond shaped epitaxy is grown from the buffer layer sidewalls. In some implementations, the diamond shaped epitaxy may be subsequently merged with surrounding dielectric. A dopant concentration of the surrounding dielectric may be higher than a dopant concentration of the diamond shaped epitaxy.

Abstract translation: 半导体结构包括半导体衬底上的翅片。 通过在翅片侧壁和翅片的上表面上形成缓冲层来提供干净的外延生长表面。 缓冲层可以外延生长。 菱形外延从缓冲层侧壁生长。 在一些实施方案中，钻石形外延可以随后与周围的电介质合并。 周围电介质的掺杂剂浓度可高于菱形外延的掺杂剂浓度。

公开(公告)号：US20160218043A1

公开(公告)日：2016-07-28

申请号：US15092233

申请日：2016-04-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L21/84 ,  H01L21/266 ,  H01L29/32 ,  H01L21/265 ,  H01L29/66

CPC classification number: H01L21/845 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L27/1211 ,  H01L29/32 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785 ,  H01L29/7856

Abstract: Merged and unmerged raised active regions on semiconductor fins can be simultaneously formed on a same substrate by control of growth rates of a deposited semiconductor material on surfaces of the semiconductor fins. In one embodiment, a growth-rate-retarding dopant can be implanted by angled ion implantation onto sidewall surfaces of first semiconductor fins on which retardation of growth rates is desired, while second semiconductor fins are masked by a masking layer. In another embodiment, a growth-rate-enhancing dopant can be implanted by ion implantation onto sidewall surfaces of second semiconductor fins, while first semiconductor fins are masked by a masking layer. The differential growth rates of the deposited semiconductor material can cause raised active regions on the first semiconductor fins to remain unmerged, and raised active regions on the second semiconductor fins to become merged.