公开(公告)号：US10510392B1

公开(公告)日：2019-12-17

申请号：US16047882

申请日：2018-07-27

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Bipul C. Paul ,  Akhilesh Jaiswal ,  Ajey Poovannummoottil Jacob ,  William Taylor ,  Danny Pak-Chum Shum

IPC: G11C11/16

Abstract: Integrated circuits, memory arrays and methods for operating integrated circuit devices are provided. In an embodiment, an integrated circuit includes a selected column of bit cells, wherein each bit cell in the selected column is coupled to a source line and coupled to a bit line. Further, the integrated circuit includes a first column of bit cells laterally adjacent the selected column, wherein each bit cell in the first column is coupled to the source line. Also, the integrated circuit includes a second column of bit cells laterally adjacent the selected column, wherein each bit cell in the second column is coupled to the bit line.

公开(公告)号：US10515679B2

公开(公告)日：2019-12-24

申请号：US15889369

申请日：2018-02-06

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Akhilesh Jaiswal ,  Ajey P. Jacob ,  Bipul C. Paul ,  William Taylor ,  Danny Pak-Chum Shum

IPC: G11C11/00 ,  G11C11/16 ,  H01L27/22 ,  H01L43/08

Abstract: A magneto-resistive memory (MRM) structure includes a source line and a first transistor that includes a source region and a drain region. The source line is electrically connected to the source region of the first transistor. The MRM structure further includes an MRM cell that includes an MRM transistor electrically in series with an MRM magnetic tunnel junction (MTJ). The MRM transistor is electrically connected to the drain region of the first transistor such that the MRM cell is electrically in series with the first transistor. Still further, the MRM structure further includes a voltage amplifier electrically connected to a mid-point node of the first transistor and the MRM transistor, a sense-amplifier electrically connected to the voltage amplifier, and a bit line electrically connected to the MRM MTJ of the MRM cell.

公开(公告)号：US10665590B2

公开(公告)日：2020-05-26

申请号：US16162373

申请日：2018-10-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  William Taylor ,  Hui Zang

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/78 ,  H01L21/8234

Abstract: The present disclosure relates to integrated circuit (IC) structures and their method of manufacture. More particularly, the present disclosure relates to forming a semiconductor device having generally fork-shaped contacts around epitaxial regions to increase surface contact area and improve device performance. The integrated circuit (IC) structure of the present disclosure comprises a plurality of fins disposed on a semiconductor substrate, at least one epitaxial region laterally disposed on selected fins, and a contact material positioned over and surrounding the epitaxial region.

公开(公告)号：US20190244650A1

公开(公告)日：2019-08-08

申请号：US15889369

申请日：2018-02-06

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Akhilesh Jaiswal ,  Ajey P. Jacob ,  Bipul C. Paul ,  William Taylor ,  Danny Pak-Chum Shum

IPC: G11C11/16 ,  H01L43/08 ,  H01L27/22

Abstract: A magneto-resistive memory (MRM) structure includes a source line and a first transistor that includes a source region and a drain region. The source line is electrically connected to the source region of the first transistor. The MRM structure further includes an MRM cell that includes an MRM transistor electrically in series with an MRM magnetic tunnel junction (MTJ). The MRM transistor is electrically connected to the drain region of the first transistor such that the MRM cell is electrically in series with the first transistor. Still further, the MRM structure further includes a voltage amplifier electrically connected to a mid-point node of the first transistor and the MRM transistor, a sense-amplifier electrically connected to the voltage amplifier, and a bit line electrically connected to the MRM MTJ of the MRM cell.