公开(公告)号：US20180130891A1

公开(公告)日：2018-05-10

申请号：US15348356

申请日：2016-11-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ja-Hyung HAN ,  Xingzhao SHI ,  Dinesh KOLI

IPC: H01L29/423 ,  H01L29/40 ,  H01L21/3105

CPC classification number: H01L29/4238 ,  H01L21/823437 ,  H01L29/401 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/51

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to gate structures with minimized gate thickness loss and methods of manufacture. The structure includes: a plurality of gate structures; a film layer provided over the gate structures and adjacent to the gate structures; and a planarized cap layer on the film and over the plurality of gate structures, the planarized cap layer having a different selectivity to slurry of a chemical mechanical polishing (CMP) process than the film.