公开(公告)号：US12107135B2

公开(公告)日：2024-10-01

申请号：US17467660

申请日：2021-09-07

申请人： Samsung Electronics Co., Ltd.

发明人： Jung Gil Yang ,  Seung Min Song ,  Soo Jin Jeong ,  Dong Il Bae ,  Bong Seok Suh

IPC分类号： H01L29/423 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/42392 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0642 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78696

摘要： A semiconductor device having a gate-all-around structure includes a first fin pattern and a second fin pattern separated by a first trench and extending in a first direction, a first nanosheet on the first fin pattern, a second nanosheet on the second fin pattern, a first fin liner extending along at least a portion of a sidewall and a bottom surface of the first trench, a first field insulation layer disposed on the first fin liner and filling a portion of the first trench, and a first gate structure overlapping an end portion of the first fin pattern and including a first gate spacer. A height from the bottom surface of the first trench to a lower surface of the first gate spacer is greater than a height from the bottom surface of the first trench to an upper surface of the first field insulation layer.

公开(公告)号：US12087723B2

公开(公告)日：2024-09-10

申请号：US18111328

申请日：2023-02-17

申请人： Infineon Technologies Austria AG

发明人： Victor Verdugo ,  Katrin Schmidt ,  Steffen Schmidt ,  Markus Schmitt

IPC分类号： H01L23/00 ,  B23K1/00 ,  H01L29/417 ,  H01L29/45 ,  H01L29/51 ,  B23K101/40

CPC分类号： H01L24/32 ,  B23K1/0016 ,  H01L24/83 ,  H01L29/41741 ,  H01L29/456 ,  H01L29/51 ,  B23K2101/40 ,  H01L2224/29083 ,  H01L2224/29166 ,  H01L2224/29184 ,  H01L2224/29205 ,  H01L2224/29209 ,  H01L2224/29211 ,  H01L2224/29213 ,  H01L2224/29217 ,  H01L2224/29218 ,  H01L2224/2922 ,  H01L2224/29239 ,  H01L2224/29244 ,  H01L2224/29247 ,  H01L2224/32227 ,  H01L2224/32245 ,  H01L2224/32503 ,  H01L2224/83201 ,  H01L2224/83203 ,  H01L2224/8321 ,  H01L2224/8381 ,  H01L2224/8382

摘要： A semiconductor assembly includes a substrate including a metal die attach surface, a semiconductor die that is arranged on the substrate, the semiconductor die being configured as a power semiconductor device and comprising a semiconductor body, a rear side metallization, and a front side layer stack, the front side layer stack comprising a front side metallization and a contaminant protection layer that is between the front side metallization and the semiconductor body, and a diffusion soldered joint between the metal die attach surface and the rear side metallization, the diffusion soldered joint comprising one or more intermetallic phases throughout the diffusion soldered joint, wherein the contaminant protection layer is configured to prevent transmission of contaminants into the semiconductor body.

公开(公告)号：US20240276714A1

公开(公告)日：2024-08-15

申请号：US18635924

申请日：2024-04-15

申请人： Micron Technology, Inc.

发明人： Toshihiko Miyashita ,  Dan Mocuta

IPC分类号： H10B12/00 ,  H01L27/092 ,  H01L29/08 ,  H01L29/167 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC分类号： H10B12/50 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/42368 ,  H01L29/51 ,  H01L29/66795 ,  H01L29/7851 ,  H10B12/09

摘要： DRAM circuitry comprises a memory array comprising memory cells individually comprising a transistor and a charge-storage device. The transistors individually comprise two source/drain regions having a gate there-between that is part of one of multiple wordlines of the memory array. One of the source/drain regions is electrically coupled to one of the charge-storage devices. The other of the source/drain regions is electrically coupled to one of multiple sense lines of the memory array. Peripheral circuitry comprises wordline-driver transistors having gates which individually comprise one of the wordlines and comprises sense-line-amplifier transistors having gates which individually comprise one of the sense lines. The sense-line-amplifier transistors and the wordline-driver transistors individually are a finFET having at least one fin comprising a channel region of the respective finFET. The sense-line-amplifier transistors and the wordline-driver transistors individually comprise two source/drain regions that individually comprise conductively-doped epitaxial semiconductor material that is adjacent one of two laterally-opposing sides of the at least one fin in a vertical cross-section. Methods are also disclosed.

公开(公告)号：US12034074B2

公开(公告)日：2024-07-09

申请号：US17516017

申请日：2021-11-01

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Marie Denison ,  Sameer Pendharkar ,  Guru Mathur

IPC分类号： H01L29/78 ,  H01L21/225 ,  H01L21/283 ,  H01L21/324 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66

CPC分类号： H01L29/7813 ,  H01L21/225 ,  H01L21/283 ,  H01L21/324 ,  H01L21/823487 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/408 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/51 ,  H01L29/511 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66734 ,  H01L29/7809 ,  H01L29/42368 ,  H01L29/4238

摘要： A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the transistor, so that each vertical drift region is bounded on at least two opposite sides by the deep trench structures. The deep trench structures are spaced so as to form RESURF regions for the drift region. Trench gates are formed in trenches in the substrate over the vertical drift regions. The body regions are located in the substrate over the vertical drift regions.

公开(公告)号：US12027629B2

公开(公告)日：2024-07-02

申请号：US18103505

申请日：2023-01-31

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chien-Ming Lai ,  Yen-Chen Chen ,  Jen-Po Huang ,  Sheng-Yao Huang ,  Hui-Ling Chen ,  Qinggang Xing ,  Ding-Lung Chen ,  Li Li Ding ,  Yao-Hung Liu

IPC分类号： H01L29/786 ,  H01L29/10 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

CPC分类号： H01L29/7869 ,  H01L29/1037 ,  H01L29/4236 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/66742

摘要： An oxide semiconductor field effect transistor (OSFET) includes a first insulating layer, a source, a drain, a U-shaped channel layer and a metal gate. The first insulating layer is disposed on a substrate. The source and the drain are disposed in the first insulating layer. The U-shaped channel layer is sandwiched by the source and the drain. The metal gate is disposed on the U-shaped channel layer, wherein the U-shaped channel layer includes at least an oxide semiconductor layer. The present invention also provides a method for forming said oxide semiconductor field effect transistor.

公开(公告)号：US11978802B2

公开(公告)日：2024-05-07

申请号：US16218493

申请日：2018-12-13

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chung-Wei Hsu ,  Chih-Hao Wang ,  Huan-Chieh Su ,  Wei-Hao Wu ,  Zhi-Chang Lin ,  Jia-Ni Yu

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/768 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

CPC分类号： H01L29/7851 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/76832 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795

摘要： Provided are FinFET devices and methods of forming the same. A dummy gate having gate spacers on opposing sidewalls thereof is formed over a substrate. A dielectric layer is formed around the dummy gate. An upper portion of the dummy gate is removed and upper portions of the gate spacers are removed, so as to form a first opening in the dielectric layer. A lower portion of the dummy gate is removed to form a second opening below the first opening. A metal layer is formed in the first and second openings. The metal layer is partially removed to form a metal gate.

公开(公告)号：US11948994B2

公开(公告)日：2024-04-02

申请号：US17531903

申请日：2021-11-22

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Byounghoon Lee ,  Jongho Park ,  Wandon Kim ,  Sangjin Hyun

IPC分类号： H01L29/49 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L21/3115 ,  H01L21/3215

CPC分类号： H01L29/4966 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/823431 ,  H01L21/82345 ,  H01L27/0886 ,  H01L29/42392 ,  H01L29/51 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7853 ,  H01L21/3115 ,  H01L21/3215

摘要： A semiconductor device includes a substrate having first and second active regions, first and second active patterns on the first and second active regions, first and second gate electrodes running across the first and second active patterns, and a high-k dielectric layer between the first active pattern and the first gate electrode and between the second active pattern and the second gate electrode. The first gate electrode includes a work function metal pattern and an electrode pattern. The second gate electrode includes a first work function metal pattern, a second work function metal pattern, and an electrode pattern. The first work function metal pattern contains the same impurity as that of the high-k dielectric layer. An impurity concentration of the first work function metal pattern of the second gate electrode is greater than that of the work function metal pattern of the first gate electrode.

公开(公告)号：US20230420570A1

公开(公告)日：2023-12-28

申请号：US18244329

申请日：2023-09-11

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Tatsuya HONDA ,  Masashi TSUBUKU ,  Yusuke NONAKA ,  Takashi SHIMAZU ,  Shunpei YAMAZAKI

IPC分类号： H01L29/786 ,  H01L29/04 ,  H01L29/24 ,  H01L29/51 ,  G02F1/1333 ,  G02F1/1337 ,  G02F1/1339 ,  G02F1/1343 ,  H01L27/12 ,  H01L29/66

CPC分类号： H01L29/7869 ,  H01L29/045 ,  H01L29/24 ,  H01L29/51 ,  G02F1/133345 ,  G02F1/1337 ,  G02F1/13394 ,  G02F1/134309 ,  H01L27/1225 ,  H01L29/66969 ,  H01L29/78696 ,  H01L21/02565

摘要： A semiconductor device includes a gate electrode, a gate insulating film which includes oxidized material containing silicon and covers the gate electrode, an oxide semiconductor film provided to be in contact with the gate insulating film and overlap with at least the gate electrode, and a source electrode and a drain electrode electrically connected to the oxide semiconductor film. In the oxide semiconductor film, a first region which is provided to be in contact with the gate insulating film and have a thickness less than or equal to 5 nm has a silicon concentration lower than or equal to 1.0 at. %, and a region in the oxide semiconductor film other than the first region has lower silicon concentration than the first region. At least the first region includes a crystal portion.

公开(公告)号：US11848211B2

公开(公告)日：2023-12-19

申请号：US18111923

申请日：2023-02-21

申请人： Kabushiki Kaisha Toshiba

发明人： Tatsuo Shimizu ,  Yukio Nakabayashi ,  Johji Nishio ,  Chiharu Ota ,  Toshihide Ito

IPC分类号： H01L21/04 ,  H01L29/06 ,  H01L29/10 ,  H01L29/51 ,  H01L29/78 ,  H01L21/02 ,  H01L29/66 ,  H01L29/16 ,  H02P27/06 ,  B61C3/00 ,  B60L50/51 ,  B66B11/04

CPC分类号： H01L21/045 ,  H01L21/0217 ,  H01L21/02164 ,  H01L21/02236 ,  H01L21/02271 ,  H01L21/046 ,  H01L21/049 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/51 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  B60L50/51 ,  B60L2210/42 ,  B61C3/00 ,  B66B11/043 ,  H02P27/06

摘要： A semiconductor device according to an embodiment includes: a silicon carbide layer; a silicon oxide layer; and a region disposed between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration equal to or more than 1×1021 cm−3. A nitrogen concentration distribution in the silicon carbide layer, the silicon oxide layer, and the region have a peak in the region, a nitrogen concentration at a first position 1 nm away from the peak to the side of the silicon oxide layer is equal to or less than 1×1018 cm−3 and a carbon concentration at the first position is equal to or less than 1×1018 cm−3, and a nitrogen concentration at a second position 1 nm away from the peak to the side of the silicon carbide layer is equal to or less than 1×1018 cm−3.

公开(公告)号：US11695053B2

公开(公告)日：2023-07-04

申请号：US17948961

申请日：2022-09-20

申请人： STMICROELECTRONICS, INC.

发明人： John H. Zhang

IPC分类号： H01L29/51 ,  H01L21/02 ,  H01L21/28 ,  H01L29/45 ,  H01L29/49 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/285 ,  H01L21/768 ,  C23C14/04 ,  C23C14/22 ,  H01L29/66

CPC分类号： H01L29/51 ,  C23C14/048 ,  C23C14/221 ,  H01L21/02521 ,  H01L21/02631 ,  H01L21/285 ,  H01L21/2855 ,  H01L21/28088 ,  H01L21/76831 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L29/456 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

摘要： Energy bands of a thin film containing molecular clusters are tuned by controlling the size and the charge of the clusters during thin film deposition. Using atomic layer deposition, an ionic cluster film is formed in the gate region of a nanometer-scale transistor to adjust the threshold voltage, and a neutral cluster film is formed in the source and drain regions to adjust contact resistance. A work function semiconductor material such as a silver bromide or a lanthanum oxide is deposited so as to include clusters of different sizes such as dimers, trimers, and tetramers, formed from isolated monomers. A type of Atomic Layer Deposition system is used to deposit on semiconductor wafers molecular clusters to form thin film junctions having selected energy gaps. A beam of ions contains different ionic clusters which are then selected for deposition by passing the beam through a filter in which different apertures select clusters based on size and orientation.