Abstract:
The present disclosure generally relates to semiconductor structures and, more particularly, to gate structures with minimized gate thickness loss and methods of manufacture. The structure includes: a plurality of gate structures; a film layer provided over the gate structures and adjacent to the gate structures; and a planarized cap layer on the film and over the plurality of gate structures, the planarized cap layer having a different selectivity to slurry of a chemical mechanical polishing (CMP) process than the film.
Abstract:
The present disclosure relates to semiconductor structures and, more particularly, to a corrosion and/or etch protection layer for contacts and interconnect metallization integration structures and methods of manufacture. The structure includes a metallization structure formed within a trench of a substrate and a layer of cobalt phosphorous (CoP) on the metallization structure. The CoP layer is structured to prevent metal migration from the metallization structure and corrosion of the metallization structure during etching processes.
Abstract:
A method and apparatus are provided for automatically controlling the position of the spray bars and nozzles and the spray flow of a CMP in-situ cleaning module. Embodiments include fixing a wafer to a CMP cleaning module, the cleaning module having a first and a second group of spray bars and nozzles, the first and second groups of spray bars and nozzles being located proximate to opposite surfaces of the wafer; cleaning one or more of the surfaces of the wafer with a chemical spray forced through at least one of the groups of spray bars and nozzles; determining a measured profile of the one or more surfaces of the wafer; comparing the measured profile against a target profile; and adjusting automatically at least one of the first and second groups of spray bars and nozzles relative to the one or more surfaces of the wafer based on the comparison.