公开(公告)号：US20170104005A1

公开(公告)日：2017-04-13

申请号：US15375890

申请日：2016-12-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Christian Haufe ,  Ingolf Lorenz ,  Michael Zier ,  Ulrich Gerhard Hensel ,  Navneet Jain

IPC: H01L27/12 ,  H01L21/84 ,  H01L29/06 ,  H01L29/49

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L29/0696 ,  H01L29/4916 ,  H01L29/78648

Abstract: An integrated circuit is provided including a semiconductor bulk substrate, a buried oxide layer formed on the semiconductor bulk substrate, a plurality of cells, each cell having a transistor device, formed over the buried oxide layer, a plurality of gate electrode lines running through the cells and providing gate electrodes for the transistor devices of the cells, and a plurality of tap cells configured for electrically contacting the semiconductor bulk substrate and arranged at positions different from positions below or above the plurality of cells having the transistor devices.

公开(公告)号：US10114919B2

公开(公告)日：2018-10-30

申请号：US15042815

申请日：2016-02-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Herbert Johannes Preuthen ,  Stefan Block ,  Ulrich Hensel ,  Christian Haufe ,  Fulvio Pugliese

IPC: G06F17/50 ,  G06F1/32

Abstract: The present disclosure provides a placing and routing method for implementing back bias in fully depleted silicon-on-insulator. In accordance with some illustrative embodiments herein, the placing and routing method comprises placing a first plurality of a standard tap well cell along a first direction, the standard tap well cell being formed by: routing a p-BIAS wire VPW and an n-BIAS wire VNW in a first a first metallization layer, and routing a power rail and a ground rail in a second metallization layer, the VPW and the VNW extending across each of the power and ground rail, wherein the VPWs of the first plurality of standard tap well cells are continuously connected and the VNWs of the first plurality of standard tap well cells are continuously connected.

公开(公告)号：US10068918B2

公开(公告)日：2018-09-04

申请号：US15375890

申请日：2016-12-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Christian Haufe ,  Ingolf Lorenz ,  Michael Zier ,  Ulrich Gerhard Hensel ,  Navneet Jain

IPC: H01L27/12 ,  H01L29/49 ,  H01L21/84 ,  H01L29/06

Abstract: An integrated circuit is provided including a semiconductor bulk substrate, a buried oxide layer formed on the semiconductor bulk substrate, a plurality of cells, each cell having a transistor device, formed over the buried oxide layer, a plurality of gate electrode lines running through the cells and providing gate electrodes for the transistor devices of the cells, and a plurality of tap cells configured for electrically contacting the semiconductor bulk substrate and arranged at positions different from positions below or above the plurality of cells having the transistor devices.

公开(公告)号：US20170235865A1

公开(公告)日：2017-08-17

申请号：US15042815

申请日：2016-02-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Herbert Johannes Preuthen ,  Stefan Block ,  Ulrich Hensel ,  Christian Haufe ,  Fulvio Pugliese

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F1/3296 ,  G06F17/5045 ,  G06F17/5068 ,  G06F17/5077 ,  H01L27/1203

Abstract: The present disclosure provides a placing and routing method for implementing back bias in fully depleted silicon-on-insulator. In accordance with some illustrative embodiments herein, the placing and routing method comprises placing a first plurality of a standard tap well cell along a first direction, the standard tap well cell being formed by: routing a p-BIAS wire VPW and an n-BIAS wire VNW in a first a first metallization layer, and routing a power rail and a ground rail in a second metallization layer, the VPW and the VNW extending across each of the power and ground rail, wherein the VPWs of the first plurality of standard tap well cells are continuously connected and the VNWs of the first plurality of standard tap well cells are continuously connected.