公开(公告)号：US10402524B2

公开(公告)日：2019-09-03

申请号：US15588984

申请日：2017-05-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Liang Cao ,  Jie Zhang ,  David N. Power ,  Eric S. Parent

IPC: G06F17/50 ,  G03F1/36

Abstract: Methods according to the disclosure include: predicting process-sensitive geometries (PSGs) in a proposed IC layout based on violations of a set of processing constraints for the proposed IC layout, the set of processing constraints being calculated with a predictive model based on a training data repository having a plurality of optical rule check (ORC) simulations for different IC layouts; identifying actual PSGs in a circuit manufactured using the proposed IC layout; determining whether the predicted PSGs correspond to the actual PSGs in the manufactured circuit as being correct; in response to the predicting being incorrect: adjusting the predictive model based on the actual PSGs, wherein the adjusting includes submitting additional ORC data to the training data repository; and flagging the proposed IC layout as incorrectly predicted; and in response to the predicting being correct, flagging the proposed IC layout as correctly predicted.

公开(公告)号：US20180322234A1

公开(公告)日：2018-11-08

申请号：US15588984

申请日：2017-05-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Liang Cao ,  Jie Zhang ,  David N. Power ,  Eric S. Parent

IPC: G06F17/50 ,  G03F1/36

CPC classification number: G06F17/5036 ,  G03F1/36 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5081 ,  G06F2217/12

Abstract: Methods according to the disclosure include: predicting process-sensitive geometries (PSGs) in a proposed IC layout based on violations of a set of processing constraints for the proposed IC layout, the set of processing constraints being calculated with a predictive model based on a training data repository having a plurality of optical rule check (ORC) simulations for different IC layouts; identifying actual PSGs in a circuit manufactured using the proposed IC layout; determining whether the predicted PSGs correspond to the actual PSGs in the manufactured circuit as being correct; in response to the predicting being incorrect: adjusting the predictive model based on the actual PSGs, wherein the adjusting includes submitting additional ORC data to the training data repository; and flagging the proposed IC layout as incorrectly predicted; and in response to the predicting being correct, flagging the proposed IC layout as correctly predicted.