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    Placing and routing method for implementing back bias in FDSOI
    1.
    发明授权
    Placing and routing method for implementing back bias in FDSOI 有权

    公开(公告)号：US10114919B2

    公开(公告)日：2018-10-30

    申请号：US15042815

    申请日：2016-02-12

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Herbert Johannes Preuthen ,  Stefan Block ,  Ulrich Hensel ,  Christian Haufe ,  Fulvio Pugliese

    IPC: G06F17/50 ,  G06F1/32

    Abstract: The present disclosure provides a placing and routing method for implementing back bias in fully depleted silicon-on-insulator. In accordance with some illustrative embodiments herein, the placing and routing method comprises placing a first plurality of a standard tap well cell along a first direction, the standard tap well cell being formed by: routing a p-BIAS wire VPW and an n-BIAS wire VNW in a first a first metallization layer, and routing a power rail and a ground rail in a second metallization layer, the VPW and the VNW extending across each of the power and ground rail, wherein the VPWs of the first plurality of standard tap well cells are continuously connected and the VNWs of the first plurality of standard tap well cells are continuously connected.

    MEMORY CELL, MEMORY DEVICE INCLUDING A PLURALITY OF MEMORY CELLS AND METHOD INCLUDING READ AND WRITE OPERATIONS AT A MEMORY CELL
    3.
    发明申请
    MEMORY CELL, MEMORY DEVICE INCLUDING A PLURALITY OF MEMORY CELLS AND METHOD INCLUDING READ AND WRITE OPERATIONS AT A MEMORY CELL 审中-公开
    存储单元，包括多个存储单元的存储器件和包括在存储器单元中的读和写操作的方法

    公开(公告)号：US20160284392A1

    公开(公告)日：2016-09-29

    申请号：US14666420

    申请日：2015-03-24

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Stefan Block ,  Juergen Dirks ,  Herbert Johannes Preuthen

    IPC: G11C11/419

    CPC classification number: G11C11/419 ,  G11C8/16 ,  G11C11/412

    Abstract: A memory cell includes an inverter loop. The inverter loop includes a plurality of inverter pairs, wherein an output of each inverter pair is connected to an input of a next inverter pair in the loop. Each inverter pair includes a first inverter and a second inverter. An input of the first inverter provides the input of the inverter pair. An output of the second inverter provides the output of the inverter pair. An output of the first inverter is connected to an input of the second inverter. The memory cell further includes a plurality of passgate transistor pairs. Each passgate transistor pair includes a first passgate transistor connected to the input of the first inverter of the inverter pair associated with the passgate transistor pair and a second passgate transistor connected to the input of the second inverter of the inverter pair associated with the passgate transistor pair.

    Abstract translation: 存储单元包括一个反相器环路。 逆变器回路包括多个反相器对，其中每个反相器对的输出连接到回路中的下一个反相器对的输入端。 每个逆变器对包括第一反相器和第二反相器。 第一反相器的输入提供逆变器对的输入。 第二反相器的输出提供逆变器对的输出。 第一反相器的输出端连接到第二反相器的输入端。 存储单元还包括多个通道晶体管对。 每个通路晶体管对包括连接到与通路晶体管对相关联的反相器对的第一反相器的输入的第一通道晶体管和连接到与通路晶体管对相关联的反相器对的第二反相器的输入的第二通道晶体管 。

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