公开(公告)号：US20190259649A1

公开(公告)日：2019-08-22

申请号：US15901411

申请日：2018-02-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Motoi ICHIHASHI ,  Atsushi OGINO

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a dual airgap structure and methods of manufacture. The structure includes: a lower metal line; a plurality of upper metal lines; and a first airgap between the lower metal line and at least one upper metal line of the plurality of upper metal lines.

公开(公告)号：US20180012648A1

公开(公告)日：2018-01-11

申请号：US15204473

申请日：2016-07-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Motoi ICHIHASHI

IPC: G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C11/418

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a static random access memory assist circuit and methods of implementation and manufacture. The structure includes at least one static random access memory (SRAM) cell and a read assist circuit structured to apply a negative voltage to the at least one SRAM cell upon asserting of a wordline of the at least one SRAM cell.

公开(公告)号：US20190333801A1

公开(公告)日：2019-10-31

申请号：US16509947

申请日：2019-07-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Motoi ICHIHASHI ,  Atsushi OGINO

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a dual airgap structure and methods of manufacture. The structure includes: a lower metal line; a plurality of upper metal lines; and a first airgap between the lower metal line and at least one upper metal line of the plurality of upper metal lines.

公开(公告)号：US20170373071A1

公开(公告)日：2017-12-28

申请号：US15193902

申请日：2016-06-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kwan-Yong LIM ,  Motoi ICHIHASHI ,  Youngtag WOO ,  Deepak NAYAK

IPC: H01L27/11 ,  H01L29/423 ,  H01L27/092 ,  H01L21/8238 ,  H01L23/528 ,  H01L29/78 ,  H01L29/417

CPC classification number: H01L27/1104 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/7827 ,  H01L29/78642

Abstract: A semiconductor memory structure includes adjacent cross-sectionally rectangular-shaped bottom source and drain electrodes, the electrodes including n-type electrode(s) and p-type electrode(s), and vertical channel transistors on one or more of the n-type electrode(s) and one or more of the p-type electrode(s); each vertical channel transistor including a vertical channel and a gate electrode wrapped therearound, some of the transistors including pull-up transistors. The semiconductor memory structure further includes a routing gate electrode for each gate electrode, and a shared contact having at least two parts, each part situated over the routing gate electrodes for the pull-up transistors. A unit semiconductor memory cell, the semiconductor memory structure and a corresponding method of forming the memory structure are also provided.