公开(公告)号：US20160163644A1

公开(公告)日：2016-06-09

申请号：US14561359

申请日：2014-12-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Youngtag WOO ,  Ryan Ryoung-han KIM

IPC: H01L23/535 ,  H01L21/285 ,  H01L21/768 ,  H01L27/11

CPC classification number: H01L23/535 ,  H01L21/28518 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823475 ,  H01L21/845 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/1104 ,  H01L27/1211 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a semiconductor device with uniform regular shaped gate contacts and the resulting device are disclosed. Embodiments include forming first and second gate electrodes adjacent one another on a substrate; forming at least one trench silicide (TS) on the substrate between the first and second gate electrodes; forming a gate contact on the first gate electrode, the gate contact having a regular shape; forming a source/drain contact on a trench silicide between the first and second gate electrodes, wherein an upper portion of the source/drain contact overlaps an upper portion of the gate contact.

Abstract translation: 公开了一种形成具有均匀的规则形状的栅极触点的半导体器件的方法以及所得到的器件。 实施例包括在基板上形成彼此相邻的第一和第二栅电极; 在所述第一和第二栅电极之间的所述衬底上形成至少一个沟槽硅化物（TS）; 在第一栅电极上形成栅极接触，栅接触具有规则形状; 在所述第一和第二栅电极之间的沟槽硅化物上形成源极/漏极接触，其中所述源极/漏极接触部的上部与所述栅极接触件的上部重叠。

公开(公告)号：US20160141291A1

公开(公告)日：2016-05-19

申请号：US14540724

申请日：2014-11-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Youngtag WOO ,  Myungjun LEE ,  Ryan Ryoung-Han KIM ,  Jongwook KYE

IPC: H01L27/11 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02

CPC classification number: H01L27/1104 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5286 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for utilizing metal segments of an additional metal layer as landing pads for vias and also as local interconnects between contacts in an IC device and resulting devices are disclosed. Embodiments include forming source/drain and gate contacts connected to transistors on a substrate in an integrated circuit device, each contact having an upper surface with a first area; forming metal segments in a plane at the upper surface of the contacts, each metal segment being in contact with one or more of the contacts and having a second area greater than the first area; and forming one or more vias between one or more of the metal segments and one or more first segments of a first metal layer.

Abstract translation: 公开了用于利用附加金属层的金属段作为通孔的着陆焊盘以及IC器件中的触点之间的局部互连以及所产生的器件的方法。 实施例包括在集成电路器件中形成连接到衬底上的晶体管的源极/漏极和栅极触点，每个触点具有带有第一区域的上表面; 在触头的上表面处的平面中形成金属段，每个金属段与一个或多个触点接触并具有大于第一区的第二区; 以及在一个或多个金属段和第一金属层的一个或多个第一段之间形成一个或多个通孔。

公开(公告)号：US20180190588A1

公开(公告)日：2018-07-05

申请号：US15399200

申请日：2017-01-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xuelian ZHU ,  Jia ZENG ,  Wenhui WANG ,  Youngtag WOO ,  Jongwook KYE

IPC: H01L23/535 ,  H01L29/417 ,  H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L23/535 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/0642 ,  H01L29/4175 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to contacts for local connections and methods of manufacture. The structure includes: at least one contact electrically shorted to a gate structure and a source/drain contact and located below a first wiring layer; and gate, source and drain contacts extending from selected gate structures and electrically connecting to the first wiring layer.

公开(公告)号：US20170373071A1

公开(公告)日：2017-12-28

申请号：US15193902

申请日：2016-06-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kwan-Yong LIM ,  Motoi ICHIHASHI ,  Youngtag WOO ,  Deepak NAYAK

IPC: H01L27/11 ,  H01L29/423 ,  H01L27/092 ,  H01L21/8238 ,  H01L23/528 ,  H01L29/78 ,  H01L29/417

CPC classification number: H01L27/1104 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/7827 ,  H01L29/78642

Abstract: A semiconductor memory structure includes adjacent cross-sectionally rectangular-shaped bottom source and drain electrodes, the electrodes including n-type electrode(s) and p-type electrode(s), and vertical channel transistors on one or more of the n-type electrode(s) and one or more of the p-type electrode(s); each vertical channel transistor including a vertical channel and a gate electrode wrapped therearound, some of the transistors including pull-up transistors. The semiconductor memory structure further includes a routing gate electrode for each gate electrode, and a shared contact having at least two parts, each part situated over the routing gate electrodes for the pull-up transistors. A unit semiconductor memory cell, the semiconductor memory structure and a corresponding method of forming the memory structure are also provided.

公开(公告)号：US20140353765A1

公开(公告)日：2014-12-04

申请号：US14461745

申请日：2014-08-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Youngtag WOO ,  Jongwook KYE ,  Dinesh SOMASEKHAR

IPC: H01L27/11 ,  H01L21/8234

CPC classification number: H01L27/1108 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/11

Abstract: Methodology enabling a generation of fins having a variable fin pitch less than 40 nm, and the resulting device are disclosed. Embodiments include: forming a hardmask on a substrate; providing first and second mandrels on the hardmask; providing a first spacer on each side of each of the first and second mandrels; removing the first and second mandrels; providing, after removal of the first and second mandrels, a second spacer on each side of each of the first spacers; and removing the first spacers.

Abstract translation: 公开了能够产生具有可变翅片间距小于40nm的翅片的方法，并且所得到的装置被公开。 实施例包括：在基板上形成硬掩模; 在硬掩模上提供第一和第二心轴; 在每个第一和第二心轴的每一侧上提供第一间隔件; 移除第一和第二心轴; 在移除所述第一和第二心轴之后，在每个所述第一间隔件的每一侧上提供第二间隔件; 并移除第一间隔物。

公开(公告)号：US20140273474A1

公开(公告)日：2014-09-18

申请号：US13799539

申请日：2013-03-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Youngtag WOO ,  Dinesh Somasekhar ,  Juhan Kim ,  Yunfei Deng ,  Jongwook Kye

IPC: H01L21/308

CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L27/0207 ,  H01L27/11

Abstract: Methodology enabling a generation of an interconnection design utilizing an SIT process is disclosed. Embodiments include: providing a hardmask on a substrate; forming a mandrel layer on the hardmask including: first and second vertical portions extending along a vertical direction and separated by a horizontal distance; and a plurality of horizontal portions extending in a horizontal direction, wherein each of the horizontal portions is positioned between the first and second vertical portions and at a different position along the vertical direction; and forming a spacer layer on outer edges of the mandrel layer.

Abstract translation: 公开了能够利用SIT过程产生互连设计的方法。 实施例包括：在基板上提供硬掩模; 在所述硬掩模上形成心轴层，包括：沿着垂直方向延伸并分开水平距离的第一和第二垂直部分; 以及沿水平方向延伸的多个水平部分，其中每个水平部分位于第一和第二垂直部分之间以及沿着垂直方向的不同位置; 以及在心轴层的外边缘上形成间隔层。