公开(公告)号：US09530488B1

公开(公告)日：2016-12-27

申请号：US15048583

申请日：2016-02-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sriram Balasubramanian ,  Vivek Joshi ,  Randy W. Mann ,  Ratheesh Ramachandran Thankalekshmi

IPC: G11C29/50 ,  G11C11/419 ,  G11C29/44

CPC classification number: G11C11/419 ,  G11C8/16 ,  G11C29/028 ,  G11C29/44 ,  G11C29/50

Abstract: At least one method, apparatus and system disclosed involves testing a dual port memory cell in a memory device. A semiconductor wafer is processed for providing a dual port memory device. An inline DC contention margin test is performed for testing a contention margin related to a write operation into a cell of the memory device. A determination is made as to whether the contention margin is within a predetermined range. A responsive action is performed in response to determining that the contention margin is outside the predetermined range.

Abstract translation: 所公开的至少一种方法，装置和系统涉及测试存储器装置中的双端口存储单元。 处理半导体晶片以提供双端口存储器件。 执行在线DC争用余量测试，用于测试与写入操作相关的争用余量到存储器件的单元中。 确定争用余额是否在预定范围内。 响应于确定争用余量在预定范围之外来执行响应动作。

公开(公告)号：US09548136B2

公开(公告)日：2017-01-17

申请号：US14664959

申请日：2015-03-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vivek Joshi ,  Sriram Balasubramanian ,  Chad Weintraub ,  Yoann Mamy Randriamihaja ,  William McMahon

IPC: G11C29/00 ,  G11C29/04 ,  G11C11/419

CPC classification number: G11C29/04 ,  G11C11/412 ,  G11C11/419 ,  G11C29/56008

Abstract: A method and an apparatus for identifying non-intrinsic defect bits from a population of failing bits for failure analysis to characterize the extrinsic failure mechanisms is provided. Embodiments include performing a failure mode test on a bank of a memory array at different low VDD; determining optimal bank size to observe plateaus of fail counts; determining fail counts of the bank at each different low VDD; determining a plateau of the fail counts; determining whether the plateau represents extrinsic bits of the bank; and submitting the extrinsic bits for root cause analysis.

Abstract translation: 提供了一种用于从用于故障分析的故障位群体中识别非本征缺陷位以表征外在故障机制的方法和装置。 实施例包括在不同的低VDD下对存储器阵列进行故障模式测试; 确定最佳银行规模以观察失败计数的平稳度; 在每个不同的低VDD处确定存储体的故障计数; 确定失败计数的高原; 确定平台是否代表银行的外在位; 并提交根本原因分析的外在位。