公开(公告)号：US20160322345A1

公开(公告)日：2016-11-03

申请号：US14699134

申请日：2015-04-29

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Chien-Hsin Lee ,  Xiangxiang Lu ,  Mahadeva Iyer Natarajan

IPC: H01L27/02 ,  H01L29/06 ,  H01L27/088

CPC classification number: H01L27/0266 ,  H01L27/0292 ,  H01L27/088 ,  H01L29/0619

Abstract: An electro-static discharge (ESD) protection transistor device includes a plurality of transistor gates that extend parallel to one another in a first direction and a plurality of source/drain diffusion areas that extend parallel to one another in a second direction perpendicular to the first direction. Each source/drain diffusion area comprises a plurality of source/drain areas disposed between respective ones of the plurality of transistor gates. The ESD protection transistor device further includes a source contact positioned over each source area of the plurality of source areas and a drain contact positioned over each drain area of the plurality of drain areas. With respect to each source/drain diffusion area of the plurality of source/drain diffusion areas, the source contacts are offset from the drain contacts with respect to the first direction.

Abstract translation: 静电放电（ESD）保护晶体管器件包括在第一方向上彼此平行延伸的多个晶体管栅极和沿垂直于第一方向的第二方向彼此平行延伸的多个源极/漏极扩散区域 方向。 每个源极/漏极扩散区域包括设置在多个晶体管栅极中的相应的晶体管栅极之间的多个源极/漏极区域。 ESD保护晶体管器件还包括位于多个源极区域的每个源极区域上的源极接触点和位于多个漏极区域的每个漏极区域上的漏极接触点。 对于多个源极/漏极扩散区域的每个源极/漏极扩散区域，源极触点相对于第一方向从漏极触点偏移。

公开(公告)号：US10741542B2

公开(公告)日：2020-08-11

申请号：US16055365

申请日：2018-08-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chien-Hsin Lee ,  Xiangxiang Lu ,  Manjunatha Prabhu ,  Mahadeva Iyer Natarajan

IPC: H01L27/02 ,  H01L29/417 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78

Abstract: High-voltage semiconductor devices with electrostatic discharge (ESD) protection and methods of fabrication are provided. The semiconductor devices include a plurality of transistors on a substrate patterned with one or more common gates extending across a portion of the substrate, and a plurality of first S/D contacts and a plurality of second S/D contacts associated with the common gate(s). The second S/D contacts are disposed over a plurality of carrier-doped regions within the substrate. One or more floating nodes are disposed above the substrate and, at least in part, between second S/D contacts to facilitate defining the plurality of carrier-doped regions within the substrate. For instance, the carrier-doped regions may be defined from a mask with a common carrier-region opening, with the floating node(s) intersecting the common carrier-region opening and facilitating defining, along with the common opening, the plurality of separate carrier-doped regions.

公开(公告)号：US10068895B2

公开(公告)日：2018-09-04

申请号：US14661202

申请日：2015-03-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chien-Hsin Lee ,  Xiangxiang Lu ,  Manjunatha Prabhu ,  Mahadeva Iyer Natarajan

IPC: H01L23/62 ,  H01L27/02 ,  H01L29/417

Abstract: High-voltage semiconductor devices with electrostatic discharge (ESD) protection and methods of fabrication are provided. The semiconductor devices include a plurality of transistors on a substrate patterned with one or more common gates extending across a portion of the substrate, and a plurality of first S/D contacts and a plurality of second S/D contacts associated with the common gate(s). The second S/D contacts are disposed over a plurality of carrier-doped regions within the substrate. One or more floating nodes are disposed above the substrate and, at least in part, between second S/D contacts to facilitate defining the plurality of carrier-doped regions within the substrate. For instance, the carrier-doped regions may be defined from a mask with a common carrier-region opening, with the floating node(s) intersecting the common carrier-region opening and facilitating defining, along with the common opening, the plurality of separate carrier-doped regions.

公开(公告)号：US09831236B2

公开(公告)日：2017-11-28

申请号：US14699134

申请日：2015-04-29

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Chien-Hsin Lee ,  Xiangxiang Lu ,  Mahadeva Iyer Natarajan

IPC: H01L23/62 ,  H01L27/02 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L27/0266 ,  H01L27/0292 ,  H01L27/088 ,  H01L29/0619

Abstract: An electro-static discharge (ESD) protection transistor device includes a plurality of transistor gates that extend parallel to one another in a first direction and a plurality of source/drain diffusion areas that extend parallel to one another in a second direction perpendicular to the first direction. Each source/drain diffusion area comprises a plurality of source/drain areas disposed between respective ones of the plurality of transistor gates. The ESD protection transistor device further includes a source contact positioned over each source area of the plurality of source areas and a drain contact positioned over each drain area of the plurality of drain areas. With respect to each source/drain diffusion area of the plurality of source/drain diffusion areas, the source contacts are offset from the drain contacts with respect to the first direction.