公开(公告)号：US20210159273A1

公开(公告)日：2021-05-27

申请号：US16691694

申请日：2019-11-22

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anuj Gupta ,  Bipul C. Paul ,  Joe A. Versaggi

IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00

Abstract: The disclosure provides a circuit structure and method to provide self-aligned contacts in a zero-via conductor layer. The structure may include a device layer including a first contact to a first source/drain region, and a second contact to a second source/drain region, the first and second source/drain regions being separated by a transistor gate. A zero-via layer of the circuit structure may include: a first via conductor positioned on the first contact and self-aligned with an overlying metal level in a first direction; and a second via conductor positioned on the second contact and self-aligned with the overlying metal level in a second direction, the second direction being orthogonal to the first direction.

公开(公告)号：US11075247B2

公开(公告)日：2021-07-27

申请号：US16691694

申请日：2019-11-22

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Anuj Gupta ,  Bipul C. Paul ,  Joe A. Versaggi

IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00

Abstract: The disclosure provides a circuit structure and method to provide self-aligned contacts in a zero-via conductor layer. The structure may include a device layer including a first contact to a first source/drain region, and a second contact to a second source/drain region, the first and second source/drain regions being separated by a transistor gate. A zero-via layer of the circuit structure may include: a first via conductor positioned on the first contact and self-aligned with an overlying metal level in a first direction; and a second via conductor positioned on the second contact and self-aligned with the overlying metal level in a second direction, the second direction being orthogonal to the first direction.