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    HIERARCHICAL MEMORY ARCHITECTURE INCLUDING ON-CHIP MULTI-BANK NON-VOLATILE MEMORY WITH LOW LEAKAGE AND LOW LATENCY
    1.
    发明申请
    HIERARCHICAL MEMORY ARCHITECTURE INCLUDING ON-CHIP MULTI-BANK NON-VOLATILE MEMORY WITH LOW LEAKAGE AND LOW LATENCY 有权

    公开(公告)号：US20250098177A1

    公开(公告)日：2025-03-20

    申请号：US18470314

    申请日：2023-09-19

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Navneet K. Jain ,  Shashank S. Nemawarkar ,  Bipul C. Paul

    IPC: H10B61/00 ,  G11C11/4074 ,  G11C11/412 ,  G11C11/56

    Abstract: A disclosed non-volatile memory (NVM) structure is implemented in a fully depleted semiconductor-on-insulator technology processing platform and includes multiple NVM banks with NVM cells including transistors. NVM banks have well regions in a substrate. Transistors of NVM cells of each NVM bank are on an insulator layer above a corresponding well region for that bank. A bias control circuit causes well regions for NVM banks in a standby state to be biased with a reverse back biasing voltage and causes a well region for an NVM bank in an operational state to be biased with a forward back biasing voltage. The bias control circuit can initiate forward back biasing during a cache data retrieval process (before NVM bank access) to ensure that the corresponding well region of an NVM bank at issue is fully biased when, following the cache data retrieval process, access to the NVM bank is still required.

    RESISTIVE MEMORY ELEMENT ARRAYS WITH SHARED ELECTRODE STRIPS
    3.
    发明公开
    RESISTIVE MEMORY ELEMENT ARRAYS WITH SHARED ELECTRODE STRIPS 审中-公开

    公开(公告)号：US20240023345A1

    公开(公告)日：2024-01-18

    申请号：US17866756

    申请日：2022-07-18

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Venkatesh Gopinath ,  Bipul C. Paul ,  Xiaoli Hu

    IPC: H01L27/24 ,  G11C13/00 ,  H01L45/00

    CPC classification number: H01L27/2472 ,  H01L27/2454 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0069 ,  H01L45/1206

    Abstract: Structures that include resistive memory elements and methods of forming a structure that includes resistive memory elements. The structure comprises a first plurality of resistive memory elements including a first plurality of bottom electrodes, a first top electrode, and a first switching layer between the first top electrode and the first plurality of bottom electrodes. The structure further comprises a second plurality of resistive memory elements including a second plurality of bottom electrodes, a second top electrode, and a second switching layer between the second top electrode and the second plurality of bottom electrodes. The first top electrode is shared by the first plurality of resistive memory elements, and the second top electrode is shared by the second plurality of resistive memory elements.

    Structures and SRAM bit cells integrating complementary field-effect transistors
    4.
    发明授权
    Structures and SRAM bit cells integrating complementary field-effect transistors 有权

    公开(公告)号：US11309319B2

    公开(公告)日：2022-04-19

    申请号：US16984468

    申请日：2020-08-04

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Randy W. Mann ,  Bipul C. Paul ,  Julien Frougier ,  Ruilong Xie

    IPC: H01L27/11 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L27/092

    Abstract: Structures and static random access memory bit cells including complementary field effect transistors and methods of forming such structures and bit cells. A first complementary field-effect transistor has a first storage nanosheet transistor, a second storage nanosheet transistor stacked over the first storage nanosheet transistor, and a first gate electrode shared by the first storage nanosheet transistor and the second storage nanosheet transistor. A second complementary field-effect transistor has a third storage nanosheet transistor, a fourth storage nanosheet transistor stacked over the third storage nanosheet transistor, and a second gate electrode shared by the third storage nanosheet transistor and the fourth storage nanosheet transistor. The first gate electrode and the second gate electrode are arranged in a spaced arrangement along a longitudinal axis. All gate electrodes of the SRAM bitcell may be arranged in a 1CPP layout.

    Memory cells with vertically overlapping wordlines
    5.
    发明授权
    Memory cells with vertically overlapping wordlines 有权

    公开(公告)号：US11227894B2

    公开(公告)日：2022-01-18

    申请号：US16668092

    申请日：2019-10-30

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Anuj Gupta ,  Bipul C. Paul

    IPC: H01L29/78 ,  H01L23/522 ,  H01L27/22 ,  H01L23/528 ,  H01L27/24

    Abstract: One illustrative device includes an array of memory cells including a first row of memory cells and a second row of memory cells adjacent the first row, a first gate structure extending along the first row, a second gate structure extending along the second row, a first wordline positioned in a first layer above the array and contacting the first gate structure, and a second wordline positioned in a second layer above the first layer and contacting the second gate structure, wherein the second wordline vertically overlaps the first wordline.

    Circuit structure and memory circuit with resistive memory elements, and related methods
    6.
    发明授权
    Circuit structure and memory circuit with resistive memory elements, and related methods 有权

    公开(公告)号：US11004509B1

    公开(公告)日：2021-05-11

    申请号：US16677790

    申请日：2019-11-08

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Steven R. Soss ,  Bipul C. Paul

    IPC: G11C13/00 ,  H01L27/24

    Abstract: The disclosure provides a circuit structure for storage and retrieval of data, and related methods. The circuit structure may include drive transistor having a source terminal, a drain terminal, and a gate terminal coupled to a word line. A first resistive memory element coupled between the source terminal of the drive transistor and a first bit line may be in a first memory state. A second resistive memory element coupled between the drain terminal of the drive transistor and a second bit line may be in a second memory state opposite the first memory state. The structure may also include a read transistor having a source terminal coupled to the drain terminal of the drive transistor, a drain terminal coupled to ground, and a gate terminal coupled to a select line.

    Bias voltage generation circuit for memory devices
    7.
    发明授权
    Bias voltage generation circuit for memory devices 有权

    公开(公告)号：US12087384B2

    公开(公告)日：2024-09-10

    申请号：US17668962

    申请日：2022-02-10

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Ming Yin ,  Bipul C. Paul ,  Nishtha Gaul ,  Shashank Nemawarkar

    IPC: G11C5/14

    CPC classification number: G11C5/147 ,  G11C5/148

    Abstract: The present disclosure relates to memory devices and, more particularly, to bias voltage generation circuit for memory devices and methods of operation. The voltage generation circuit includes: an internal voltage generator which providing a bias voltage to at least one internal node of a bias voltage generation circuitry; and at least one pre-charging circuitry providing a predefined bias voltage to at least one internal node including a distributed network of local drivers.

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