公开(公告)号：US12288782B2

公开(公告)日：2025-04-29

申请号：US17679655

申请日：2022-02-24

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Juhan Kim ,  Sangmoon J. Kim ,  Mahbub Rashed ,  Navneet K. Jain

IPC: H01L27/02 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/118 ,  H01L29/417

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to cell layouts in semiconductor structures and methods of manufacture. A structure includes: a plurality of abutting cells each of which include transistors with gate structures having diffusion regions; a contact spanning across abutting cells of the plurality of abutting cells and contacting to the diffusion regions of separate cells of the abutting cells; and a continuous active region spanning across the plurality of abutting cells, wherein the continuous active region includes a drain-source abutment with L-shape construct, a source-source abutment with U-shape construct, and a drain-drain abutment with a filler cell located between a drain-drain abutment.

公开(公告)号：US20250118245A1

公开(公告)日：2025-04-10

申请号：US18482114

申请日：2023-10-06

Applicant: GlobalFoundries U.S. Inc.

Inventor： Juhan Kim ,  Sanjay Raj Parihar ,  Mahbub Rashed ,  Zahir Yilmaz Alpaslan

IPC: G09G3/32 ,  G11C11/419 ,  H10B10/00

Abstract: Disclosed are a pixel and a compact memory-in-pixel display (e.g., implemented in a fully-depleted semiconductor-on-insulator processing technology platform). A block of electronic components for a pixel includes a memory cell array, a driving circuit for an LED, and a logic circuit connected between the memory cell array and driving circuit. The memory cell array is above a Pwell, the driving circuit is above an adjacent Nwell, and the logic circuit includes P-type transistors on the Nwell and N-type transistors on the Pwell. A pixel array is above alternating P and N wells with a single buried Nwell below. Specifically, each column of pixels is above adjacent elongated P and N wells and, within each column, adjacent pixels have mirrored layouts. Furthermore, adjacent columns of pixels are above two elongated wells of one type and a shared elongated well of the opposite type therebetween and the adjacent columns have mirrored layouts.

公开(公告)号：US20250120175A1

公开(公告)日：2025-04-10

申请号：US18482107

申请日：2023-10-06

Applicant: GlobalFoundries U.S. Inc.

Inventor： Navneet K. Jain ,  Juhan Kim ,  Mahbub Rashed

IPC: H01L27/118 ,  H03K19/20

Abstract: Disclosed is a fully depleted semiconductor-on-insulator structure including a buried Nwell in a substrate below P-type and N-type well regions, an insulator layer on the substrate, and mixed threshold voltage transistors on the insulator layer above at least one of the well regions. An Nwell can be connected to receive a positive bias voltage with any NFET and any PFET above being a FBB LVT/SLVT NFET and a RBB RVT/HVT PFET, respectively. A Pwell can be connected to receive another positive bias voltage less than the positive bias voltage on the Nwell with any NFET and any PFET above being a FBB RVT/HVT NFET and a RBB LVT/SLVT PFET, respectively. Additionally, or alternatively, a Pwell can be connected to receive a negative bias voltage with any NFET and any PFET above being a RBB RVT/HVT NFET and a FBB LVT/SLVT PFET, respectively.

公开(公告)号：US12272299B1

公开(公告)日：2025-04-08

申请号：US18482114

申请日：2023-10-06

Applicant: GlobalFoundries U.S. Inc.

Inventor： Juhan Kim ,  Sanjay Raj Parihar ,  Mahbub Rashed ,  Zahir Yilmaz Alpaslan

IPC: G09G3/32 ,  G11C11/419 ,  H10B10/00

Abstract: Disclosed are a pixel and a compact memory-in-pixel display (e.g., implemented in a fully-depleted semiconductor-on-insulator processing technology platform). A block of electronic components for a pixel includes a memory cell array, a driving circuit for an LED, and a logic circuit connected between the memory cell array and driving circuit. The memory cell array is above a Pwell, the driving circuit is above an adjacent Nwell, and the logic circuit includes P-type transistors on the Nwell and N-type transistors on the Pwell. A pixel array is above alternating P and N wells with a single buried Nwell below. Specifically, each column of pixels is above adjacent elongated P and N wells and, within each column, adjacent pixels have mirrored layouts. Furthermore, adjacent columns of pixels are above two elongated wells of one type and a shared elongated well of the opposite type therebetween and the adjacent columns have mirrored layouts.