公开(公告)号：US20250118245A1

公开(公告)日：2025-04-10

申请号：US18482114

申请日：2023-10-06

Applicant: GlobalFoundries U.S. Inc.

Inventor： Juhan Kim ,  Sanjay Raj Parihar ,  Mahbub Rashed ,  Zahir Yilmaz Alpaslan

IPC: G09G3/32 ,  G11C11/419 ,  H10B10/00

Abstract: Disclosed are a pixel and a compact memory-in-pixel display (e.g., implemented in a fully-depleted semiconductor-on-insulator processing technology platform). A block of electronic components for a pixel includes a memory cell array, a driving circuit for an LED, and a logic circuit connected between the memory cell array and driving circuit. The memory cell array is above a Pwell, the driving circuit is above an adjacent Nwell, and the logic circuit includes P-type transistors on the Nwell and N-type transistors on the Pwell. A pixel array is above alternating P and N wells with a single buried Nwell below. Specifically, each column of pixels is above adjacent elongated P and N wells and, within each column, adjacent pixels have mirrored layouts. Furthermore, adjacent columns of pixels are above two elongated wells of one type and a shared elongated well of the opposite type therebetween and the adjacent columns have mirrored layouts.

公开(公告)号：US12272299B1

公开(公告)日：2025-04-08

申请号：US18482114

申请日：2023-10-06

Applicant: GlobalFoundries U.S. Inc.

Inventor： Juhan Kim ,  Sanjay Raj Parihar ,  Mahbub Rashed ,  Zahir Yilmaz Alpaslan

IPC: G09G3/32 ,  G11C11/419 ,  H10B10/00

Abstract: Disclosed are a pixel and a compact memory-in-pixel display (e.g., implemented in a fully-depleted semiconductor-on-insulator processing technology platform). A block of electronic components for a pixel includes a memory cell array, a driving circuit for an LED, and a logic circuit connected between the memory cell array and driving circuit. The memory cell array is above a Pwell, the driving circuit is above an adjacent Nwell, and the logic circuit includes P-type transistors on the Nwell and N-type transistors on the Pwell. A pixel array is above alternating P and N wells with a single buried Nwell below. Specifically, each column of pixels is above adjacent elongated P and N wells and, within each column, adjacent pixels have mirrored layouts. Furthermore, adjacent columns of pixels are above two elongated wells of one type and a shared elongated well of the opposite type therebetween and the adjacent columns have mirrored layouts.