公开(公告)号：US20230112377A1

公开(公告)日：2023-04-13

申请号：US17496296

申请日：2021-10-07

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Kaustubh Shanbhag ,  Eric S. Kozarsky ,  George R. Mulfinger ,  Jianwei Peng

IPC: H01L27/12 ,  H01L21/84

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to semiconductor devices with a shared common backside well and methods of manufacture. The structure includes: adjacent gate structures over a semiconductor substrate; a common well in the semiconductor substrate under the adjacent gate structures; a deep trench isolation structure extending through the common well between the adjacent gate structures; and a shared diffusion region between the adjacent gate structures.

公开(公告)号：US20240282852A1

公开(公告)日：2024-08-22

申请号：US18171765

申请日：2023-02-21

Applicant: GlobalFoundries U.S. Inc.

Inventor： Shesh Mani Pandey ,  Kaustubh Shanbhag ,  Rajendran Krishnasamy ,  Judson R. Holt

IPC: H01L29/78 ,  H01L21/306 ,  H01L21/308 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L21/30604 ,  H01L21/308 ,  H01L29/0642 ,  H01L29/66681

Abstract: Disclosed are embodiments of a structure including a semiconductor layer and a device, which has a well region within the semiconductor layer and at least one porous region within and shallower in depth than the well region. In some embodiments, the device can be a field effect transistor (FET) (e.g., a laterally diffused metal oxide semiconductor field effect transistor (LDMOSFETs)) with a drain drift region that extends through the well region around the porous region(s) to a drain region. The porous region(s) can modify the electric field in this drain drift region, thereby improving device performance. Embodiments can vary with regard to the number, size, shape, configuration, etc. of the porous region(s) within the well region. Also disclosed herein are method embodiments for forming the semiconductor structure.

公开(公告)号：US11749671B2

公开(公告)日：2023-09-05

申请号：US17067033

申请日：2020-10-09

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Kaustubh Shanbhag ,  Glenn Workman

IPC: H01L27/02 ,  H01L21/8238 ,  H01L21/762

CPC classification number: H01L27/0207 ,  H01L21/7624 ,  H01L21/823892

Abstract: The disclosure provides integrated circuit (IC) structures and methods to form the same. Methods according to the disclosure may be performed on a substrate having a first doping type, the substrate extending between a first end and a second end. A deep well is formed within the substrate, the deep well including a well boundary defined between the deep well and a remainder of the substrate. The well boundary is horizontally distal to a midpoint between the first end and the second end of the substrate. A first active semiconductor region is formed at least partially over the substrate, and an oppositely-doped second active semiconductor region is formed at least partially over the deep well.

公开(公告)号：US20220115368A1

公开(公告)日：2022-04-14

申请号：US17067033

申请日：2020-10-09

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Kaustubh Shanbhag ,  Glenn Workman

IPC: H01L27/02 ,  H01L21/762 ,  H01L21/8238

Abstract: The disclosure provides integrated circuit (IC) structures and methods to form the same. Methods according to the disclosure may be performed on a substrate having a first doping type, the substrate extending between a first end and a second end. A deep well is formed within the substrate, the deep well including a well boundary defined between the deep well and a remainder of the substrate. The well boundary is horizontally distal to a midpoint between the first end and the second end of the substrate. A first active semiconductor region is formed at least partially over the substrate, and an oppositely-doped second active semiconductor region is formed at least partially over the deep well.

公开(公告)号：US11798948B2

公开(公告)日：2023-10-24

申请号：US17496296

申请日：2021-10-07

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Kaustubh Shanbhag ,  Eric S. Kozarsky ,  George R. Mulfinger ,  Jianwei Peng

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/762 ,  H01L29/808

CPC classification number: H01L27/1203 ,  H01L21/7624 ,  H01L21/84 ,  H01L29/808

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to semiconductor devices with a shared common backside well and methods of manufacture. The structure includes: adjacent gate structures over a semiconductor substrate; a common well in the semiconductor substrate under the adjacent gate structures; a deep trench isolation structure extending through the common well between the adjacent gate structures; and a shared diffusion region between the adjacent gate structures.

公开(公告)号：US11721621B2

公开(公告)日：2023-08-08

申请号：US17527606

申请日：2021-11-16

Applicant: GlobalFoundries U.S. Inc.

Inventor： Shweta Vasant Khokale ,  Kaustubh Shanbhag ,  Tamilmani Ethirajan

IPC: H01L23/522 ,  H01L27/12 ,  H01L21/84 ,  H01L23/528

CPC classification number: H01L23/5225 ,  H01L21/84 ,  H01L23/5226 ,  H01L23/5286 ,  H01L27/1203

Abstract: Structures including stacked field-effect transistors and methods of forming a structure including stacked field-effect transistors. The structure includes a field-effect transistor having a first active gate, a second active gate, and a drain region that is positioned in a horizontal direction between the first and second active gates. The structure further includes a back-end-of-line stack having a first metal level and a second metal level over the field-effect transistor. The first metal level includes a first interconnect, a second interconnect, and a third interconnect, and the second metal level includes a fourth interconnect. The third interconnect is connected to the drain region. The third interconnect is positioned in a vertical direction between the fourth interconnect and the drain region, and the third interconnect is positioned in the horizontal direction between the first and second interconnects.

公开(公告)号：US20230154844A1

公开(公告)日：2023-05-18

申请号：US17527606

申请日：2021-11-16

Applicant: GlobalFoundries U.S. Inc.

Inventor： Shweta Vasant Khokale ,  Kaustubh Shanbhag ,  Tamilmani Ethirajan

IPC: H01L23/522 ,  H01L27/12 ,  H01L23/528 ,  H01L21/84

CPC classification number: H01L23/5225 ,  H01L27/1203 ,  H01L23/5226 ,  H01L23/5286 ,  H01L21/84

Abstract: Structures including stacked field-effect transistors and methods of forming a structure including stacked field-effect transistors. The structure includes a field-effect transistor having a first active gate, a second active gate, and a drain region that is positioned in a horizontal direction between the first and second active gates. The structure further includes a back-end-of-line stack having a first metal level and a second metal level over the field-effect transistor. The first metal level includes a first interconnect, a second interconnect, and a third interconnect, and the second metal level includes a fourth interconnect. The third interconnect is connected to the drain region. The third interconnect is positioned in a vertical direction between the fourth interconnect and the drain region, and the third interconnect is positioned in the horizontal direction between the first and second interconnects.