公开(公告)号：US20240339503A1

公开(公告)日：2024-10-10

申请号：US18624483

申请日：2024-04-02

Applicant: UIF (University Industry Foundation), Yonsei University

Inventor： Dae Hong KO ,  Chung Hee CHO ,  Ki Seok LEE ,  Dong Min YOON

IPC: H01L29/165 ,  H01L21/225 ,  H01L21/308

CPC classification number: H01L29/165 ,  H01L21/2251 ,  H01L21/308

Abstract: An epitaxial wafer is disclosed. The epitaxial wafer includes a substrate; and a stack structure disposed on the substrate, wherein the stack structure includes first and second layers alternately stacked on top of each other, wherein the first layer is made of a compound represented by one selected from a group consisting of following Chemical Formulas 1-1 to 1-5, wherein the second layer is made of a compound represented by a following Chemical Formula 2:


Si1-xGex(m≤x≤1.0)  [Chemical Formula 1-1]



Si1-x-yGexBy(m≤x

公开(公告)号：US20240334671A1

公开(公告)日：2024-10-03

申请号：US18735797

申请日：2024-06-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ta-Chun LIN ,  Kuo-Hua PAN

IPC: H10B10/00 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H10B10/125 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/82385 ,  H01L21/823864 ,  H01L21/823878 ,  H01L27/0922 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first device formed over a substrate, and the first device comprises a first channel structure. The semiconductor device structure includes a first gate stack wrapped around the first channel structure, and a second device formed over the first device. The second device comprises a plurality of second nanostructures stacked in a vertical direction. The semiconductor device structure include a second gate stack wrapped around the second nanostructures, and a portion of the first gate stack is higher than a topmost second nanostructure.

公开(公告)号：US20240332062A1

公开(公告)日：2024-10-03

申请号：US18741166

申请日：2024-06-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hsien-Chung HUANG ,  Chiung-Wen HSU ,  Mei-Ju KUO ,  Yu-Ting WENG ,  Yu-Chi LIN ,  Ting-Chung WANG ,  Chao-Cheng CHEN

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L21/76232 ,  H01L21/0259 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/78696

Abstract: A device includes a substrate, a first fin, a second fin, a first isolation structure, a second isolation structure, and a gate structure. The first fin extends from a p-type region of the substrate. The second fin extends from an n-type region of the substrate. The first isolation structure is over the p-type region and adjacent to the first fin. The first isolation structure has a bottom surface and opposite first and second sidewalls connected to the bottom surface, a first round corner is between the bottom surface and the first sidewall of the first isolation structure, and the first sidewall is substantially parallel to the second sidewall. The second isolation structure is over the n-type region and adjacent to the first fin. The first isolation structure is deeper than the second isolation structure. The gate structure is over the first isolation structure and covering the first fin.

公开(公告)号：US20240297106A1

公开(公告)日：2024-09-05

申请号：US18177953

申请日：2023-03-03

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Michael J. SEDDON ,  Francis J. CARNEY

IPC: H01L23/498 ,  H01L21/02 ,  H01L21/288 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/48 ,  H01L21/56 ,  H01L21/66 ,  H01L21/67 ,  H01L21/683 ,  H01L21/768 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/482 ,  H01L23/495 ,  H01L23/544 ,  H01L25/00 ,  H01L25/065 ,  H01L27/02 ,  H01L27/088 ,  H01L27/14 ,  H01L27/146 ,  H01L29/08 ,  H02M3/158

CPC classification number: H01L23/49827 ,  H01L21/02035 ,  H01L21/288 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3083 ,  H01L21/4825 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/565 ,  H01L21/67069 ,  H01L21/6835 ,  H01L21/76877 ,  H01L21/76898 ,  H01L21/78 ,  H01L22/12 ,  H01L22/26 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/4822 ,  H01L23/49503 ,  H01L23/4951 ,  H01L23/49541 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/544 ,  H01L23/562 ,  H01L24/00 ,  H01L24/05 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/14 ,  H01L27/14683 ,  H01L29/0847 ,  H02M3/158 ,  H01L23/147 ,  H01L23/15 ,  H01L23/3677 ,  H01L23/49816 ,  H01L27/14625 ,  H01L27/14685 ,  H01L2221/68327 ,  H01L2223/54426 ,  H01L2223/5446 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05172 ,  H01L2224/05184 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2225/06555 ,  H01L2225/06593 ,  H01L2225/06596 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/3511

Abstract: A through-substrate via structure includes a conductive via structure including trench portions at a first major surface of a substrate and extending to a first distance. A first insulating structure is over sidewalls of the trench portions, and a conductive material is over the first insulating structure. A recessed region extends from a second major surface of the substrate to a second distance greater than the first distance and laterally overlaps and interfaces both trench portions. A second insulating structure includes a first portion within the recessed region and a second portion adjacent to the second major surface outside of the recessed region, which includes an outer surface overlapping the second major surface outside of the recessed region. A first conductive region includes a proximate end coupled to the conductive material through openings in the first portion, and an opposite distal that is outward from the second portion.

公开(公告)号：US12074213B2

公开(公告)日：2024-08-27

申请号：US17357697

申请日：2021-06-24

Applicant: The Board of Trustees of the University of Illinois

Inventor： Ralph G. Nuzzo ,  John A. Rogers ,  Etienne Menard ,  Keon Jae Lee ,  Dahl-Young Khang ,  Yugang Sun ,  Matthew Meitl ,  Zhengtao Zhu

IPC: H01L29/76 ,  B82Y10/00 ,  H01L21/02 ,  H01L21/308 ,  H01L21/322 ,  H01L21/683 ,  H01L23/00 ,  H01L23/02 ,  H01L25/075 ,  H01L27/12 ,  H01L29/04 ,  H01L29/06 ,  H01L29/12 ,  H01L29/786 ,  H01L31/0392 ,  H01L31/18 ,  H01L33/00 ,  H01L33/32

CPC classification number: H01L29/76 ,  B82Y10/00 ,  H01L21/02521 ,  H01L21/02603 ,  H01L21/02628 ,  H01L21/308 ,  H01L21/322 ,  H01L21/6835 ,  H01L23/02 ,  H01L24/03 ,  H01L24/80 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0753 ,  H01L27/1285 ,  H01L27/1292 ,  H01L29/04 ,  H01L29/06 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/12 ,  H01L29/78603 ,  H01L29/78681 ,  H01L29/78696 ,  H01L31/0392 ,  H01L31/03926 ,  H01L31/1804 ,  H01L31/1864 ,  H01L31/1896 ,  H01L33/007 ,  H01L33/0093 ,  H01L33/32 ,  B81C2201/0185 ,  H01L24/05 ,  H01L24/08 ,  H01L24/29 ,  H01L24/32 ,  H01L24/94 ,  H01L2221/68368 ,  H01L2221/68381 ,  H01L2224/03 ,  H01L2224/0332 ,  H01L2224/0345 ,  H01L2224/03614 ,  H01L2224/0362 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05644 ,  H01L2224/05666 ,  H01L2224/08225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/80 ,  H01L2224/80006 ,  H01L2224/80121 ,  H01L2224/80862 ,  H01L2224/80895 ,  H01L2224/83 ,  H01L2224/83005 ,  H01L2224/83121 ,  H01L2224/83192 ,  H01L2224/83193 ,  H01L2224/8385 ,  H01L2224/83862 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2224/97 ,  H01L2924/00012 ,  H01L2924/01032 ,  H01L2924/0665 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/12044 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13063 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15159 ,  H01L2924/15162 ,  H01L2924/15788 ,  H01L2924/1579 ,  Y02E10/547 ,  Y02P70/50 ,  Y10S977/707 ,  Y10S977/724 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05124 ,  H01L2924/00014 ,  H01L2224/0332 ,  H01L2924/00014 ,  H01L2224/97 ,  H01L2224/80 ,  H01L2224/97 ,  H01L2224/83 ,  H01L2224/80121 ,  H01L2924/00012 ,  H01L2224/83121 ,  H01L2924/00012 ,  H01L2224/9202 ,  H01L2224/03 ,  H01L2224/05666 ,  H01L2924/00014 ,  H01L2224/2919 ,  H01L2924/0665 ,  H01L2224/94 ,  H01L2224/03 ,  H01L2224/05155 ,  H01L2924/00014 ,  H01L2224/05144 ,  H01L2924/01032 ,  H01L2224/05082 ,  H01L2224/05644 ,  H01L2224/05155 ,  H01L2224/05144 ,  H01L2924/01032 ,  H01L2224/05073 ,  H01L2224/05644 ,  H01L2224/05166 ,  H01L2224/05166 ,  H01L2924/00014 ,  H01L2224/05555 ,  H01L2924/00014 ,  H01L2224/05554 ,  H01L2924/00014 ,  H01L2224/05553 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2924/00012 ,  H01L2224/83192 ,  H01L2224/32225 ,  H01L2924/00 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/1306 ,  H01L2924/00 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2924/1305 ,  H01L2924/00 ,  H01L2924/12032 ,  H01L2924/00 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2924/12036 ,  H01L2924/00 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2924/12043 ,  H01L2924/00 ,  H01L2924/12044 ,  H01L2924/00 ,  H01L2924/13063 ,  H01L2924/00 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/13055 ,  H01L2924/00

Abstract: The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.

公开(公告)号：US20240260249A1

公开(公告)日：2024-08-01

申请号：US18608199

申请日：2024-03-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hao Lin ,  Kian-Long Lim ,  Chih-Chuan Yang ,  Chia-Hao Pao ,  Jing-Yi Lin

IPC: H10B10/00 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H10B10/125 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: A substrate includes a first doped region having a first type dopant, and a second doped region having a second type dopant and adjacent to the first doped region. A stack is formed that includes first layers and second layers alternating with each other. The first and second layers each have a first and second semiconductor material, respectively. The second semiconductor material is different than the first semiconductor material. A mask element is formed that has an opening in a channel region over the second doped region. A top portion of the stack not covered by the mask element is recessed. The stack is then processed to form a first and a second transistors. The first transistor has a first number of first layers. The second transistor has a second number of first layers. The first number is greater than the second number.

公开(公告)号：US20240242969A1

公开(公告)日：2024-07-18

申请号：US18619304

申请日：2024-03-28

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Wayne CHEN ,  Andrew P. EDWARDS ,  Clifford DROWLEY ,  Subhash Srinivas PIDAPARTHI

IPC: H01L21/306 ,  H01L21/308 ,  H01L21/66 ,  H01L29/20 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/30612 ,  H01L21/308 ,  H01L22/26 ,  H01L29/2003 ,  H01L29/66522 ,  H01L29/66666 ,  H01L29/7827

Abstract: A method of manufacturing a vertical FET device includes providing a semiconductor substrate structure including a marker layer; forming a hardmask layer coupled to the semiconductor substrate structure, wherein the hardmask layer comprises a set of openings operable to expose an upper surface portion of the semiconductor substrate structure; etching the upper surface portion of the semiconductor substrate structure to form a plurality of fins; etching at least a portion of the marker layer; detecting the etching of the at least a portion of the marker layer; epitaxially growing a semiconductor layer in recess regions disposed between adjacent fins of the plurality of fins; forming a source metal layer on each of the plurality of fins; and forming a gate metal layer coupled to the semiconductor layer.

公开(公告)号：US12029025B2

公开(公告)日：2024-07-02

申请号：US17839047

申请日：2022-06-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ta-Chun Lin ,  Kuo-Hua Pan

IPC: H10B10/00 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H10B10/125 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/82385 ,  H01L21/823864 ,  H01L21/823878 ,  H01L27/0922 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first device formed over a substrate, wherein the first device includes a first fin structure and a first S/D structure formed over the first fin structure. The semiconductor device structure includes a second device formed over or below the first device, and the second device includes a plurality of second nanostructures stacked in a vertical direction. The semiconductor device structure also includes a second S/D structure formed over the second nanostructures, and the second S/D structure is directly above or below the first S/D structure.

公开(公告)号：US11967626B2

公开(公告)日：2024-04-23

申请号：US17474699

申请日：2021-09-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Mitsuhiro Togo ,  Takashi Kobayashi ,  Sudarshan Narayanan

IPC: H01L29/00 ,  H01L21/306 ,  H01L21/308 ,  H01L29/40 ,  H01L29/423 ,  H10B41/41 ,  H10B43/40

CPC classification number: H01L29/4236 ,  H01L21/30608 ,  H01L21/308 ,  H01L29/401 ,  H01L29/42376 ,  H10B41/41 ,  H10B43/40

Abstract: A field effect transistor includes at least one line trench extending downward from a top surface of a channel region which laterally surrounds or underlies the at least one line trench, a gate dielectric contacting all surfaces of the at least one line trench and including a planar gate dielectric portion that extends over an entirety of a top surface of the channel region, a gate electrode, a source region, and a drain region.

公开(公告)号：US11959004B2

公开(公告)日：2024-04-16

申请号：US17339474

申请日：2021-06-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Simon Joshua Jacobs

IPC: C09K13/02 ,  C09K13/00 ,  H01L21/306 ,  H01L21/308

CPC classification number: C09K13/02 ,  C09K13/00 ,  H01L21/30604 ,  H01L21/308

Abstract: An alkaline etching solution comprising a hydroxide salt (e.g., an alkali metal hydroxide, an ammonium hydroxide, or a combination thereof), a polyol having at least three hydroxyl (—OH) groups, and water. Also provided is a method of producing a semiconductor device by obtaining a semiconductor substrate having masked and unmasked surfaces; exposing the semiconductor substrate having the masked and unmasked surfaces to an alkaline etching solution, such that the unmasked surfaces of the substrate are anisotropically etched, wherein the alkaline etching solution comprises: a hydroxide salt; a polyol having at least three hydroxyl (—OH) groups; and water; and performing additional processing to produce the semiconductor device.