公开(公告)号：US20230178289A1

公开(公告)日：2023-06-08

申请号：US17543808

申请日：2021-12-07

Applicant: GlobalFoundries U.S. Inc.

Inventor： Varuna A. Baipadi ,  Venkata Narayana Rao Vanukuru ,  Muhammed Shafi Kunnathodi

IPC: H01F27/28 ,  H01F3/14

CPC classification number: H01F27/2804 ,  H01F3/14 ,  H01F2027/2809

Abstract: A structure includes a first layer having inductor windings. An inner area of the first layer is at least partially enclosed by the inductor windings and an outer area of the first layer is separated from the inner area by the inductor windings. This structure further includes a second layer having structural fill elements. The first layer and the second layer are parallel, and the second layer is relatively below the first layer in a direction perpendicular to the first layer. The density of the structural fill elements aligned below the inner area is less than the density of the structural fill elements aligned below the outer area.

公开(公告)号：US12211886B1

公开(公告)日：2025-01-28

申请号：US18765489

申请日：2024-07-08

Applicant: GlobalFoundries U.S. Inc.

Inventor： Prateek Kumar Sharma ,  Venkata Narayana Rao Vanukuru ,  Kevin K. Dezfulian ,  Kenneth J. Giewont

IPC: H01L21/768 ,  H01L21/764 ,  H01L49/02

Abstract: Structures including an inductor and methods of forming such structures. The structure comprises a semiconductor substrate including a first plurality of sealed cavities and a back-end-of-line stack on the semiconductor substrate. Each sealed cavity includes an air gap, and the back-end-of-line stack includes an inductor having a winding that overlaps with the scaled cavities.

公开(公告)号：US20240243175A1

公开(公告)日：2024-07-18

申请号：US18098188

申请日：2023-01-18

Applicant: GlobalFoundries U.S. Inc.

Inventor： Venkata Narayana Rao Vanukuru ,  Steven M. Shank

IPC: H01L29/10 ,  H01L21/74 ,  H01L27/12

CPC classification number: H01L29/1087 ,  H01L21/743 ,  H01L27/1203

Abstract: Structures including a field-effect transistor field-effect and methods of forming a structure including a field-effect transistor. The structure comprises a trench isolation region in a substrate, and a body contact region that extends through the trench isolation region to the substrate. The structure further comprises a field-effect transistor including a gate connector, a first gate finger that extends from the gate connector, a second gate finger that extends from the gate connector, and a source/drain region disposed between the first gate finger and the second gate finger. The gate connector is positioned over the trench isolation region. The structure further comprises a gate contact coupled to the gate connector, and a body contact that penetrates through a portion of the gate connector to the body contact region.

公开(公告)号：US11942423B2

公开(公告)日：2024-03-26

申请号：US17343101

申请日：2021-06-09

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Venkata Narayana Rao Vanukuru ,  Zhong-Xiang He

IPC: H01L23/522 ,  H01F17/00 ,  H01F41/04 ,  H01L23/528

CPC classification number: H01L23/5227 ,  H01F17/0013 ,  H01F41/041 ,  H01L23/5283

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to series inductors and methods of manufacture. A structure includes a plurality of wiring levels each of which include a wiring structure connected in series to one another. A second wiring level being located above a first wiring level of the plurality of wiring levels. A wiring structure on the second wiring level being at least partially outside boundaries of the wiring structure of the first wiring level.