公开(公告)号：US20240282853A1

公开(公告)日：2024-08-22

申请号：US18111995

申请日：2023-02-21

Applicant: GlobalFoundries U.S. Inc.

Inventor： Shesh Mani PANDEY ,  Rajendran KRISHNASAMY ,  Chung Foong TAN

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/7825 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/66704

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a device with workfunction metal in a drift region and methods of manufacture. The structure includes: a gate structure having at least a first workfunction metal in a channel region and a second workfunction metal, which is different from the first workfunction metal, in a trench in a drift region; and a sidewall spacer adjacent to the gate structure within the trench in the drift region.

公开(公告)号：US20240282847A1

公开(公告)日：2024-08-22

申请号：US18111959

申请日：2023-02-21

Applicant: GlobalFoundries U.S. Inc.

Inventor： Shesh Mani PANDEY ,  Sagar Premnath KARALKAR ,  Rajendran KRISHNASAMY ,  Chung Foong TAN

IPC: H01L29/74 ,  H01L29/66

CPC classification number: H01L29/74 ,  H01L29/66363

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to high performance silicon controlled rectifier (SCR) devices and methods of manufacture. The structure includes: a first well in a semiconductor substrate; a second well in the semiconductor substrate, adjacent to the first well; and a porous semiconductor region extending in the first well and the second well.

公开(公告)号：US20240162345A1

公开(公告)日：2024-05-16

申请号：US17984736

申请日：2022-11-10

Applicant: GlobalFoundries U.S. Inc.

Inventor： Shesh M. PANDEY ,  Rajendran KRISHNASAMY ,  Judson R. HOLT ,  Chung Foong TAN

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/7823 ,  H01L21/76224 ,  H01L29/401 ,  H01L29/407 ,  H01L29/66681

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a transistor with a metal field plate contact and methods of manufacture. The structure includes: a gate structure on a semiconductor substrate; a shallow trench isolation structure within the semiconductor substrate; and a contact extending from the gate structure and into the shallow trench isolation structure.