公开(公告)号：US20240195416A1

公开(公告)日：2024-06-13

申请号：US18064978

申请日：2022-12-13

Applicant: GlobalFoundries U.S. Inc.

Inventor： Dzung T. Tran ,  Deepti A. Pant ,  Shibly S. Ahmed

IPC: H03K19/003

CPC classification number: H03K19/00361 ,  H03K19/00315

Abstract: Disclosed is an input buffer with hysteresis-integrated voltage protection devices for avoiding violations of maximum gate-to-source voltage limitations when the maximum input voltage is greater than the maximum gate-to-source voltage limitation. The input buffer includes a chain of transistors including two P-channel FETs (PFETs) and two N-channel FETs (NFETs). The data input to the input buffer controls the gates of the transistors in the chain so the data output from the input buffer at the junction between the PFETs and NFETs is inverted. The input buffer also includes a hysteresis feedback loop to prevent noise-induced switching of the output. The hysteresis feedback loop also includes voltage protection devices integrated therein to avoid maximum gate-to-source violations when the loop results in a hysteresis voltage being fed back into the chain at the source region of a transistor in the chain. Also disclosed is a receiver incorporating the input buffer.

公开(公告)号：US11368155B1

公开(公告)日：2022-06-21

申请号：US17112456

申请日：2020-12-04

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Dzung T. Tran ,  Shibly S. Ahmed

IPC: H03K19/0175 ,  H03K19/0185 ,  H03K19/20 ,  H03K19/003

Abstract: Embodiments of the disclosure provide an input output (IO) structure in which complimentary nodes of a level shifter are utilized to logically block the output of the IO structure from switching until both power supplies to the IO structure are powered up. An illustrative level shifter includes: a cross-coupled pair of PFETs configured to output complimentary voltage values at a first node and a second node; a control circuit configured to select which of the complementary voltage values are output to the first node and second node; a logic inverter having an input coupled to the first node and an output coupled to a third node; and a NAND gate having inputs coupled to the second node and third node and that generates a level shifted output.

公开(公告)号：US20220182058A1

公开(公告)日：2022-06-09

申请号：US17112456

申请日：2020-12-04

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Dzung T. Tran ,  Shibly S. Ahmed

IPC: H03K19/0185 ,  H03K19/20

Abstract: Embodiments of the disclosure provide an input output (IO) structure in which complimentary nodes of a level shifter are utilized to logically block the output of the IO structure from switching until both power supplies to the IO structure are powered up. An illustrative level shifter includes: a cross-coupled pair of PFETs configured to output complimentary voltage values at a first node and a second node; a control circuit configured to select which of the complementary voltage values are output to the first node and second node; a logic inverter having an input coupled to the first node and an output coupled to a third node; and a NAND gate having inputs coupled to the second node and third node and that generates a level shifted output.